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2019-10-29arm64: tegra: Fix compatible string for EQOS on Tegra194Thierry Reding1-1/+2
The EQOS Ethernet controller found on Tegra194 is compatible with its predecessor or Tegra186. However, it is an established practice to add a compatible string for the most recent generation of the SoC as well, just in case some incompatibilities or bugs are later discovered. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERMThierry Reding1-1/+3
For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix base address for SOR1 on Tegra194Thierry Reding1-1/+1
The SOR1 hardware block's registers start at physical address 0x15b40000 as correctly specified by the unit-address, but the reg property lists a wrong value, likely because it was copy-and-pasted from SOR0 but not correctly updated. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add unit-address for ACONNECT on Tegra194Thierry Reding2-2/+2
The ACONNECT complex starts at physical address 0x2900000, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add unit-address for CBB on Tegra194Thierry Reding3-12/+12
The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add CPU and cache topology for Tegra194Thierry Reding1-12/+144
Tegra194 has four CPU clusters, each with their own cache hierarchy. This patch creates the CPU map for these clusters and adds the second- and third-level caches and associates them with the CPUs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix 'active-low' warning for Jetson Xavier regulatorJon Hunter1-2/+1
Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") added regulators for the PCIe slot on the Jetson Xavier platform. One of these regulators has an active-low enable and this commit incorrectly added an active-low specifier for the GPIO which causes the following warning to occur on boot ... WARNING KERN regulator@3 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier. Finally, remove the 'enable-active-low' as this is not a valid property. Fixes: 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix 'active-low' warning for Jetson TX1 regulatorJon Hunter1-1/+1
Commit 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") added a regulator for HDMI on the Jetson TX1 platform. This regulator has an active high enable, but the GPIO specifier for enabling the regulator incorrectly defines it as active-low. This causes the following warning to occur on boot ... WARNING KERN regulator@10 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier which aligns with the presense of the 'enable-active-high' property. Fixes: 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: cardhu-a04: Add CPU Operating Performance PointsDmitry Osipenko1-0/+24
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on Cardhu A04. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: cardhu-a04: Set up voltage regulators for DVFSDmitry Osipenko1-0/+24
Set minimum and maximum voltages, and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: trimslice: Add CPU Operating Performance PointsDmitry Osipenko1-0/+11
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available now on TrimSlice. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: paz00: Add CPU Operating Performance PointsDmitry Osipenko1-0/+14
Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on AC100. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: paz00: Set up voltage regulators for DVFSDmitry Osipenko1-7/+20
Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add CPU Operating Performance Points for Tegra30Dmitry Osipenko2-0/+2003
Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary for them. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add CPU Operating Performance Points for Tegra20Dmitry Osipenko2-0/+503
Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary, like for example in a case of tegra20-trimslice which is outlet-powered device. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add Tegra30 CPU clockDmitry Osipenko1-0/+4
All "geared" CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add Tegra20 CPU clockDmitry Osipenko1-0/+2
All CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add External Memory Controller node on Tegra30Dmitry Osipenko1-0/+9
Add External Memory Controller node to the device-tree. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6Dmitry Osipenko1-1621/+6248
Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1, which was missed due to the clock driver bug that is fixed now in all of stable kernels. Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30Dmitry Osipenko1-0/+1
Enable IOMMU support for the video decoder. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add eDP power supplies on Venice2Thierry Reding1-0/+3
The power supplies needed to drive eDP on Venice2 were never hooked up, so things only worked because those regulators are already enabled by other devices. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add SOR0_OUT clock on Tegra124Thierry Reding1-1/+2
This clock is needed for eDP to properly function, so add it to the SOR device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add stmpe-adc DT node to Toradex T30 modulesPhilippe Schenker3-24/+42
Add the stmpe-adc DT node as found on Toradex T30 modules Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29RISC-V: Issue a tlb page flush if possibleAtish Patra1-1/+4
If tlbflush request is for page only, there is no need to do a complete local tlb shootdown. Just do a local tlb flush for the given address. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-29RISC-V: Issue a local tlbflush if possible.Atish Patra1-2/+17
In RISC-V, tlb flush happens via SBI which is expensive. If the local cpu is the only cpu in cpumask, there is no need to invoke a SBI call. Just do a local flush and return. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-29RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra1-0/+3
SBI calls are expensive. If cpumask is empty, there is no need to trap via SBI as no remote tlb flushing is required. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-29riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov5-3/+63
This patch was extensively tested on Fedora/RISCV (applied by default on top of 5.2-rc7 kernel for <2 months). The patch was also tested with 5.3-rc on QEMU and SiFive Unleashed board. libseccomp (userspace) was rebased: https://github.com/seccomp/libseccomp/pull/134 Fully passes libseccomp regression testing (simulation and live). There is one failing kernel selftest: global.user_notification_signal v1 -> v2: - return immediately if secure_computing(NULL) returns -1 - fixed whitespace issues - add missing seccomp.h - remove patch #2 (solved now) - add riscv to seccomp kernel selftest Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Cc: keescook@chromium.org Cc: me@carlosedp.com Tested-by: Carlos de Paula <me@carlosedp.com> Reviewed-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/linux-riscv/CAEn-LTp=ss0Dfv6J00=rCAy+N78U2AmhqJNjfqjr2FDpPYjxEQ@mail.gmail.com/ Link: https://lore.kernel.org/linux-riscv/CAJr-aD=UnCN9E_mdVJ2H5nt=6juRSWikZnA5HxDLQxXLbsRz-w@mail.gmail.com/ [paul.walmsley@sifive.com: cleaned up Cc: lines; fixed spelling and checkpatch issues; updated to apply] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-29arm64: cpufeature: Enable Qualcomm Falkor/Kryo errata 1003Bjorn Andersson1-0/+1
With the introduction of 'cce360b54ce6 ("arm64: capabilities: Filter the entries based on a given mask")' the Qualcomm Falkor/Kryo errata 1003 is no long applied. The result of not applying errata 1003 is that MSM8996 runs into various RCU stalls and fails to boot most of the times. Give 1003 a "type" to ensure they are not filtered out in update_cpu_capabilities(). Fixes: cce360b54ce6 ("arm64: capabilities: Filter the entries based on a given mask") Cc: stable@vger.kernel.org Reported-by: Mark Brown <broonie@kernel.org> Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Will Deacon <will@kernel.org>
2019-10-29arm64: Ensure VM_WRITE|VM_SHARED ptes are clean by defaultCatalin Marinas1-7/+8
Shared and writable mappings (__S.1.) should be clean (!dirty) initially and made dirty on a subsequent write either through the hardware DBM (dirty bit management) mechanism or through a write page fault. A clean pte for the arm64 kernel is one that has PTE_RDONLY set and PTE_DIRTY clear. The PAGE_SHARED{,_EXEC} attributes have PTE_WRITE set (PTE_DBM) and PTE_DIRTY clear. Prior to commit 73e86cb03cf2 ("arm64: Move PTE_RDONLY bit handling out of set_pte_at()"), it was the responsibility of set_pte_at() to set the PTE_RDONLY bit and mark the pte clean if the software PTE_DIRTY bit was not set. However, the above commit removed the pte_sw_dirty() check and the subsequent setting of PTE_RDONLY in set_pte_at() while leaving the PAGE_SHARED{,_EXEC} definitions unchanged. The result is that shared+writable mappings are now dirty by default Fix the above by explicitly setting PTE_RDONLY in PAGE_SHARED{,_EXEC}. In addition, remove the superfluous PTE_DIRTY bit from the kernel PROT_* attributes. Fixes: 73e86cb03cf2 ("arm64: Move PTE_RDONLY bit handling out of set_pte_at()") Cc: <stable@vger.kernel.org> # 4.14.x- Cc: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2019-10-29um-ubd: Entrust re-queue to the upper layersAnton Ivanov1-2/+6
Fixes crashes due to ubd requeue logic conflicting with the block-mq logic. Crash is reproducible in 5.0 - 5.3. Fixes: 53766defb8c8 ("um: Clean-up command processing in UML UBD driver") Cc: stable@vger.kernel.org # v5.0+ Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-10-29arm64: print additional fault message when executing non-exec memoryXiang Zheng1-0/+2
When attempting to executing non-executable memory, the fault message shows: Unable to handle kernel read from unreadable memory at virtual address ffff802dac469000 This may confuse someone, so add a new fault message for instruction abort. Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-10-29ARM: tegra: Use WFE for power-gating on Tegra30Dmitry Osipenko1-1/+3
Turned out that WFI doesn't work reliably on Tegra30 as a trigger for the power-gating, it causes CPU hang under some circumstances like having memory controller running of PLLP. The TRM doc states that WFI should be used for the Big-Little "Cluster Switch", while WFE for the power-gating. Hence let's use the WFE for CPU0 power-gating, like it is done for the power-gating of a secondary cores. This fixes CPU hang after entering LP2 with memory running off PLLP. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Fix FLOW_CTLR_HALT register clobbering by tegra_resume()Dmitry Osipenko1-3/+3
There is an unfortunate typo in the code that results in writing to FLOW_CTLR_HALT instead of FLOW_CTLR_CSR. Cc: <stable@vger.kernel.org> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Enable Tegra VDE driver in tegra_defconfigDmitry Osipenko1-0/+2
The video decoder driver was tested by time and works absolutely fine. The reason why it is in staging is because it doesn't provide common V4L interface yet, this shouldn't stop driver enabling in the defconfig since our userspace (libvdpau-tegra) provides combined acceleration of decoding and displaying without use of V4L. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29powerpc/powernv: Fix CPU idle to be called with IRQs disabledNicholas Piggin1-16/+37
Commit e78a7614f3876 ("idle: Prevent late-arriving interrupts from disrupting offline") changes arch_cpu_idle_dead to be called with interrupts disabled, which triggers the WARN in pnv_smp_cpu_kill_self. Fix this by fixing up irq_happened after hard disabling, rather than requiring there are no pending interrupts, similarly to what was done done until commit 2525db04d1cc5 ("powerpc/powernv: Simplify lazy IRQ handling in CPU offline"). Fixes: e78a7614f3876 ("idle: Prevent late-arriving interrupts from disrupting offline") Reported-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Add unexpected_mask rather than checking for known bad values, change the WARN_ON() to a WARN_ON_ONCE()] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20191022115814.22456-1-npiggin@gmail.com
2019-10-29context_tracking: Rename context_tracking_is_enabled() => context_tracking_enabled()Frederic Weisbecker1-1/+1
Remove the superfluous "is" in the middle of the name. We want to standardize the naming so that it can be expanded through suffixes: context_tracking_enabled() context_tracking_enabled_cpu() context_tracking_enabled_this_cpu() Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Jacek Anaszewski <jacek.anaszewski@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rafael J . Wysocki <rjw@rjwysocki.net> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Wanpeng Li <wanpengli@tencent.com> Cc: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Link: https://lkml.kernel.org/r/20191016025700.31277-6-frederic@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-10-29ARM: sunxi: Fix CPU powerdown on A83TOndrej Jirman1-1/+5
PRCM_PWROFF_GATING_REG has CPU0 at bit 4 on A83T. So without this patch, instead of gating the CPU0, the whole cluster was power gated, when shutting down first CPU in the cluster. Fixes: 6961275e72a8c1 ("ARM: sun8i: smp: Add support for A83T") Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Cc: stable@vger.kernel.org Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-29ARM: dts: sun8i-a83t-tbs-a711: Fix WiFi resume from suspendOndrej Jirman1-0/+1
Without enabling keep-power-in-suspend, we can't wake the device up using WOL packet, and the log is flooded with these messages on resume: sunxi-mmc 1c10000.mmc: send stop command failed sunxi-mmc 1c10000.mmc: data error, sending stop command sunxi-mmc 1c10000.mmc: send stop command failed sunxi-mmc 1c10000.mmc: data error, sending stop command So to make the WiFi really a wakeup-source, we need to keep it powered during suspend. Fixes: 0e23372080def7 ("arm: dts: sun8i: Add the TBS A711 tablet devicetree") Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-29arm64: dts: realtek: Add RTD129x UART resetsAndreas Färber1-0/+4
Associate the UART nodes with the corresponding reset controller bits. Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29arm64: dts: realtek: Add RTD129x reset controller nodesAndreas Färber1-0/+30
Add nodes for the Realtek RTD1295 reset controllers. Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29powerpc/prom_init: Undo relocation before entering secure modeThiago Jung Bauermann3-1/+18
The ultravisor will do an integrity check of the kernel image but we relocated it so the check will fail. Restore the original image by relocating it back to the kernel virtual base address. This works because during build vmlinux is linked with an expected virtual runtime address of KERNELBASE. Fixes: 6a9c930bd775 ("powerpc/prom_init: Add the ESM call to prom_init") Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Tested-by: Michael Anderson <andmike@linux.ibm.com> [mpe: Add IS_ENABLED() to fix the CONFIG_RELOCATABLE=n build] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190911163433.12822-1-bauerman@linux.ibm.com
2019-10-29arm64: dts: realtek: Add watchdog node for RTD129xAndreas Färber1-0/+6
Add the watchdog node to the RTD129x Device Tree. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Guenter Roeck <linux@roeck-us.net> [AF: Moved from RTD1295 to new RTD129x] Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29arm64: dts: realtek: Add oscillator for RTD129xAndreas Färber1-0/+7
Add 27 MHz oscillator clock node. Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29arm64: dts: realtek: Add RTD1296 and Synology DS418Andreas Färber3-0/+97
Add Device Trees for RTD1296 SoC and Synology DiskStation DS418. Cc: info@synology.com Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29arm64: dts: realtek: Add RTD1293 and Synology DS418jAndreas Färber3-0/+84
Add Device Trees for RTD1293 SoC and Synology DiskStation DS418j NAS. Cc: info@synology.com Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29arm64: dts: realtek: Change dual-license from MIT to BSDAndreas Färber3-6/+3
Move the SPDX-License-Identifier to the top line and update to SPDX 2.0. While at it, switch from GPLv2+/MIT to GPLv2+/BSD2c before adding more. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2019-10-29ARM: imx_v6_v7_defconfig: Enable CONFIG_TOUCHSCREEN_DA9052Fabio Estevam1-0/+1
Enable the CONFIG_TOUCHSCREEN_DA9052 option, so that touchscreen can be functional by default on imx53-qsb. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-29arm64: defconfig: Enable configs for S32V234Mihaela Martinas1-0/+3
Enable support for the S32V234 SoC, including the previously added UART driver. Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Signed-off-by: Adrian.Nitu <adrian.nitu@freescale.com> Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-29arm64: defconfig: Enable CONFIG_KEYBOARD_IMX_SC_KEY as moduleAnson Huang1-0/+1
Select CONFIG_KEYBOARD_IMX_SC_KEY as module by default to support i.MX8QXP scu key driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28Merge tag 'arc-5.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arcLinus Torvalds3-2/+31
Pull ARC fixes from Vineet Gupta: "Small fixes for ARC: - perf fix for Big Endian build [Alexey] - hadk platform enable soem peripherals [Eugeniy]" * tag 'arc-5.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: perf: Accommodate big-endian CPU ARC: [plat-hsdk]: Enable on-boardi SPI ADC IC ARC: [plat-hsdk]: Enable on-board SPI NOR flash IC
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