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2019-10-28ARC: mm: tlb flush optim: elide redundant uTLB invalidates for MMUv3Vineet Gupta1-5/+0
For MMUv3 (and prior) the flush_tlb_{range,mm,page} API use the MMU TLBWrite cmd which already nukes the entire uTLB, so NO need for additional IVUTLB cmd from utlb_invalidate() - hence this patch local_flush_tlb_all() is special since it uses a weaker TLBWriteNI cmd (prec commit) to shoot down JTLB, hence we retain the explicit uTLB flush Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: mm: tlb flush optim: elide repeated uTLB invalidate in loopVineet Gupta1-45/+29
The unconditional full TLB flush (on say ASID rollover) iterates over each entry and uses TLBWrite to zero it out. TLBWrite by design also invalidates the uTLBs thus we end up invalidating it as many times as numbe rof entries (512 or 1k) Optimize this by using a weaker TLBWriteNI cmd in loop, which doesn't tinker with uTLBs and an explicit one time IVUTLB, outside the loop to invalidate them all once. And given the optimiztion, the IVUTLB is now needed on MMUv4 too where the uTLBs and JTLBs are otherwise coherent given the TLBInsertEntry / TLBDeleteEntry commands Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: mm: tlb flush optim: Make TLBWriteNI fallback to TLBWrite if not availableVineet Gupta2-4/+2
TLBWriteNI was introduced in MMUv2 (to not invalidate uTLBs in Fast Path TLB Refill Handler). To avoid #ifdef'ery make it fallback to TLBWrite availabel on all MMUs. This will also help with next change Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: mm: TLB Miss optim: avoid re-reading ECRVineet Gupta1-2/+0
For setting PTE Dirty bit, reuse the prior test for ST miss. No need to reload ECR and test for ST cause code as the prev condition code is still valid (uncloberred) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARCv2: mm: TLB Miss optim: Use double world load/stores LDD/STDVineet Gupta1-0/+10
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch regVineet Gupta6-6/+10
ARC700 exception (and intr handling) didn't have auto stack switching thus had to rely on stashing a reg temporarily (to free it up) at a known place in memory, allowing to code up the low level stack switching. This however was not re-entrant in SMP which thus had to repurpose the per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg pointer (vs. reading it from mm struct) The newer HS cores do have auto-stack switching and thus even SMP builds can use the MMU SCRATCH reg as originally intended. This patch fixes the restriction to ARC700 SMP builds only Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: nSIM_700: remove unused network optionsEugeniy Paltsev2-18/+2
We have snps,arc-emac enabled in nSIM_700. It's obsolete and it's not used anymore so remove its device tree node and disable unused network options in defconfig. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: nSIM_700: switch to DW UART usageEugeniy Paltsev2-11/+17
Switch nsim_700_defconfig to dwuart for consistent uart settings for all nSIM configurations. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: merge HAPS-HS with nSIM-HS configsEugeniy Paltsev6-244/+1
Starting from nSIM 2019.06 is possible to use DW UART instead of ARC UART. That allows us to merge "nsim_hs" with "haps_hs" and "nsim_hs_smp" with "haps_hs_smp" with minor changes which were done in previous commits. We eliminate nsim_hs_defconfig and nsim_hs_smp_defconfig and leave haps_hs_defconfig and haps_hs_smp_defconfig which can be used on HAPS / nSIM / ZEBU / QEMU platforms without additional changes in Linux kernel. For nSIM we should now use UART property values "-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000" instead of previously used "-prop=nsim_mem-dev=uart0,base=0xc0fc1000" "use_connect" and "irq" values of UART property remains untouched. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: HAPS: cleanup defconfigs from unused ETH driversEugeniy Paltsev2-20/+2
We have multiple vendors ethernet drivers enabled in haps_hs and haps_hs_smp defconfig. The only one we possibly require is VIRTIO_NET. So disable unused ones via disabling entire CONFIG_ETHERNET which controls all vendor-specific ethernet drivers. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: HAPS: add HIGHMEM memory zone to DTSEugeniy Paltsev1-5/+8
This is required as a preparation of merging nSIM and HASP defonfig and device tree. As we have HIGHMEM disabled in both HAPS and nSIM defconfigs this doesn't lead to any functional change. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: HAPS: use same UART configuration everywhereEugeniy Paltsev2-2/+1
For some reason we use ns8250 UART compatible on UP HAPS configuration and ns16550a (which is ns8250 with FIFO support) on SMP HAPS configuration. Given that we have same UART IP with same IP configuration on both HAPS configuration use ns16550a compatible everywhere. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: HAPS: cleanup defconfigs from unused IO-related optionsEugeniy Paltsev2-12/+6
We don't have any peripherals on HAPS which may require FB or input_devices support. So get rid of them. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28ARC: regenerate nSIM and HAPS defconfigsEugeniy Paltsev5-35/+12
No functional change intended. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28RISC-V: Remove unsupported isa string info printAtish Patra1-42/+3
/proc/cpuinfo should just print all the isa string as an information instead of determining what is supported or not. ELF hwcap can be used by the userspace to figure out that. Simplify the isa string printing by removing the unsupported isa string print and all related code. The relevant discussion can be found at http://lists.infradead.org/pipermail/linux-riscv/2019-September/006702.html Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Link: http://lists.infradead.org/pipermail/linux-riscv/2019-September/006702.html Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-28RISC-V: Add PCIe I/O BAR memory mappingYash Shah2-1/+13
For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux, we need to establish a reserved memory region for them, so that drivers that wish to use the legacy I/O BARs can issue reads and writes against a memory region that is mapped to the host PCIe controller's I/O BAR mapping. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-28ARM: exynos: Enable exynos-asv driver for ARCH_EXYNOSSylwester Nawrocki1-0/+1
Enable exynos-asv driver for Exynos 32-bit SoCs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-28Merge branch 'for-next/entry-s-to-c' into for-next/coreCatalin Marinas14-358/+417
Move the synchronous exception paths from entry.S into a C file to improve the code readability. * for-next/entry-s-to-c: arm64: entry-common: don't touch daif before bp-hardening arm64: Remove asmlinkage from updated functions arm64: entry: convert el0_sync to C arm64: entry: convert el1_sync to C arm64: add local_daif_inherit() arm64: Add prototypes for functions called by entry.S arm64: remove __exception annotations
2019-10-28ARM: s3c: Rename s5p_usb_phy functionsKrzysztof Kozlowski3-6/+6
The name s5p_usb_phy_init() suggests it is shared with S5Pv210 platform, but it is not. It is specific to S3C64xx, so make it clear in the name. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-28ARM: s3c: Rename s3c64xx_spi_setname() functionKrzysztof Kozlowski3-3/+3
The name s3c64xx_spi_setname() suggests it is shared with S3C64xx platform, but except of contents it is not. It is called only by S3C24xx code, so make it clear in the name. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-28arm64: Make arm64_dma32_phys_limit staticCatalin Marinas1-1/+1
This variable is only used in the arch/arm64/mm/init.c file for ZONE_DMA32 initialisation, no need to expose it. Reported-by: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-10-28Merge branch 'kvm-arm64/erratum-1319367' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into for-next/coreCatalin Marinas6-12/+120
Similarly to erratum 1165522 that affects Cortex-A76, A57 and A72 respectively suffer from errata 1319537 and 1319367, potentially resulting in TLB corruption if the CPU speculates an AT instruction while switching guests. The fix is slightly more involved since we don't have VHE to help us here, but the idea is the same: when switching a guest in, we must prevent any speculated AT from being able to parse the page tables until S2 is up and running. Only at this stage can we allow AT to take place. For this, we always restore the guest sysregs first, except for its SCTLR and TCR registers, which must be set with SCTLR.M=1 and TCR.EPD{0,1} = {1, 1}, effectively disabling the PTW and TLB allocation. Once S2 is setup, we restore the guest's SCTLR and TCR. Similar things must be done on TLB invalidation... * 'kvm-arm64/erratum-1319367' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms: arm64: Enable and document ARM errata 1319367 and 1319537 arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs arm64: KVM: Reorder system register restoration and stage-2 activation arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions
2019-10-28KVM: arm64: Don't set HCR_EL2.TVM when S2FWB is supportedChristoffer Dall2-3/+12
On CPUs that support S2FWB (Armv8.4+), KVM configures the stage 2 page tables to override the memory attributes of memory accesses, regardless of the stage 1 page table configurations, and also when the stage 1 MMU is turned off. This results in all memory accesses to RAM being cacheable, including during early boot of the guest. On CPUs without this feature, memory accesses were non-cacheable during boot until the guest turned on the stage 1 MMU, and we had to detect when the guest turned on the MMU, such that we could invalidate all cache entries and ensure a consistent view of memory with the MMU turned on. When the guest turned on the caches, we would call stage2_flush_vm() from kvm_toggle_cache(). However, stage2_flush_vm() walks all the stage 2 tables, and calls __kvm_flush-dcache_pte, which on a system with S2FWB does ... absolutely nothing. We can avoid that whole song and dance, and simply not set TVM when creating a VM on a system that has S2FWB. Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20191028130541.30536-1-christoffer.dall@arm.com
2019-10-28Merge branch 'for-next/neoverse-n1-stale-instr' into for-next/coreCatalin Marinas6-3/+71
Neoverse-N1 cores with the 'COHERENT_ICACHE' feature may fetch stale instructions when software depends on prefetch-speculation-protection instead of explicit synchronization. [0] The workaround is to trap I-Cache maintenance and issue an inner-shareable TLBI. The affected cores have a Coherent I-Cache, so the I-Cache maintenance isn't necessary. The core tells user-space it can skip it with CTR_EL0.DIC. We also have to trap this register to hide the bit forcing DIC-aware user-space to perform the maintenance. To avoid trapping all cache-maintenance, this workaround depends on a firmware component that only traps I-cache maintenance from EL0 and performs the workaround. For user-space, the kernel's work is to trap CTR_EL0 to hide DIC, and produce a fake IminLine. EL3 traps the now-necessary I-Cache maintenance and performs the inner-shareable-TLBI that makes everything better. [0] https://developer.arm.com/docs/sden885747/latest/arm-neoverse-n1-mp050-software-developer-errata-notice * for-next/neoverse-n1-stale-instr: arm64: Silence clang warning on mismatched value/register sizes arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419 arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419
2019-10-28Merge tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dtOlof Johansson16-50/+171
STM32 DT updates for v5.5, round 1 Highlights: ---------- MPU part: -Add and enable ADC support on stm32mp157a-dk1 -Add DAC support on stm32mp157c-ed1 -Add and enable VREFBUF support on stm32mp157a-dk1 -Add focaltech touchscreen on stm32mp157c-dk2 -Add hdmi support on stm32mp157a-dk1 -Fix issues seen during YAML DT validation -Fix regulators issues for all MPU boards MCU part: -Fix issues seen during YAML DT validation * tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: remove useless dma-ranges property for stm32f469 ARM: dts: stm32: remove useless dma-ranges property for stm32f429 ARM: dts: stm32: disable active-discharge for vbus_otg on stm32mp157a-avenger96 ARM: dts: stm32: Fix active discharge usage on stm32mp157 ARM: dts: stm32: change default minimal buck1 value on stm32mp157 ARM: dts: stm32: add PWR regulators support on stm32mp157 ARM: dts: stm32: remove useless interrupt from dsi node for stm32f469 ARM: dts: stm32: add hdmi audio support to stm32mp157a-dk1 board ARM: dts: stm32: Add DAC support to stm32mp157c-ed1 ARM: dts: stm32: Add DAC pins used on stm32mp157c-ed1 ARM: dts: stm32: fix regulator-sd_switch node on stm32mp157c-ed1 board ARM: dts: stm32: remove usb phy-names entries on stm32mp157c-ev1 ARM: dts: stm32: fix joystick node on stm32f746 and stm32mp157c eval boards ARM: dts: stm32: fix memory nodes to match with DT validation tool ARM: dts: stm32: add focaltech touchscreen on stm32mp157c-dk2 board ARM: dts: stm32: enable ADC support on stm32mp157a-dk1 ARM: dts: stm32: add ADC pins used on stm32mp157a-dk1 ARM: dts: stm32: Enable VREFBUF on stm32mp157a-dk1 ARM: dts: stm32: move ltdc pinctrl on stm32mp157a dk1 board Link: https://lore.kernel.org/r/02c39510-f36d-abbb-c76f-49aff07c0a08@st.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-28Merge tag 'juno-update-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dtOlof Johansson1-0/+27
ARMv8 Juno update for v5.5 Single patch to add support for Mali GPU on all versions of Juno. Though it's disabled by default, it is very useful to test panfrost drivers. * tag 'juno-update-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: add GPU subsystem Link: https://lore.kernel.org/r/20191028040022.GC20568@e107533-lin.cambridge.arm.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-28Merge remote-tracking branch 'arm64/for-next/fixes' into for-next/coreCatalin Marinas13-23/+183
This is required to solve the conflicts with subsequent merges of two more errata workaround branches. * arm64/for-next/fixes: arm64: tags: Preserve tags for addresses translated via TTBR1 arm64: mm: fix inverted PAR_EL1.F check arm64: sysreg: fix incorrect definition of SYS_PAR_EL1_F arm64: entry.S: Do not preempt from IRQ before all cpufeatures are enabled arm64: hibernate: check pgd table allocation arm64: cpufeature: Treat ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled arm64: Fix kcore macros after 52-bit virtual addressing fallout arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected arm64: Avoid Cavium TX2 erratum 219 when switching TTBR arm64: Enable workaround for Cavium TX2 erratum 219 when running SMT arm64: KVM: Trap VM ops when ARM64_WORKAROUND_CAVIUM_TX2_219_TVM is set
2019-10-28KVM: arm/arm64: Show halt poll counters in debugfsChristian Borntraeger2-0/+8
ARM/ARM64 has counters halt_successful_poll, halt_attempted_poll, halt_poll_invalid, and halt_wakeup but never exposed those in debugfs. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1572164390-5851-1-git-send-email-borntraeger@de.ibm.com
2019-10-28arm64: dts: imx8mn: Add LPDDR4 EVK board supportAnson Huang2-0/+31
i.MX8MN LPDDR4 EVK board shares most of the device as DDR4 EVK board, the ONLY difference are the DDR type and PMIC, add support for it and make it default i.MX8MN EVK board as usual. The PMIC driver is NOT ready, so cpu-freq needs to be disabled as it depends on regulator provided by PMIC. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mn: Create EVK dtsi file for common useAnson Huang2-240/+253
i.MX8MN has different EVK boards to support different DDR types, the ONLY differences are DDR chips and PMIC, so most of the devices can be shared between these EVK boards, create a EVK dtsi file for common use. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mn: Move usdhc clocks assignment to board DTAnson Huang2-4/+4
usdhc's clock rate is different according to different devices connected, so clock rate assignment should be placed in board DT according to different devices connected on each usdhc port. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mm: Move usdhc clocks assignment to board DTAnson Huang2-4/+4
usdhc's clock rate is different according to different devices connected, so clock rate assignment should be placed in board DT according to different devices connected on each usdhc port. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mq: Move usdhc clocks assignment to board DTAnson Huang8-2/+22
usdhc's clock rate is different according to different devices connected, so clock rate assignment should be placed in board DT according to different devices connected on each usdhc port. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8qxp: Move usdhc clocks assignment to board DTAnson Huang3-6/+8
usdhc's clock rate is different according to different devices connected, so clock rate assignment should be placed in board DT according to different devices connected on each usdhc port. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: fsl: Add device tree for S32V234-EVBStoica Cosmin-Stefan3-0/+166
Add initial version of device tree for S32V234-EVB, including nodes for the 4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and Generic Interrupt Controller (GIC). Keep SoC level separate from board level to let future boards with this SoC share common properties, while the dts files will keep board-dependent properties. Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Signed-off-by: Dan Nica <dan.nica@nxp.com> Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com> Signed-off-by: Phu Luu An <phu.luuan@nxp.com> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mm-evk: Assigned clocks for audio pllsS.j. Wang2-2/+8
Assign clocks and clock-rates for audio plls, that audio drivers can utilize them. Add dai-tdm-slot-num and dai-tdm-slot-width for sound-wm8524, that sai driver can generate correct bit clock. Fixes: 13f3b9fdef6c ("arm64: dts: imx8mm-evk: Enable audio codec wm8524") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: zii-ultra: Add node for switch watchdogAndrey Smirnov1-0/+5
Add I2C node for switch watchdog present on both Zest and RMB3 boards. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: zii-ultra: Add node for accelerometerAndrey Smirnov1-0/+18
Add I2C node for accelerometer present on both Zest and RMB3 boards. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: zii-ultra: Fix regulator-3p3-main's nameAndrey Smirnov1-1/+1
It's 3V3_MAIN, not 3V3V_MAIN on schematic. Fix it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: zii-ultra: Fix regulator-vsd-3v3's vin-supplyAndrey Smirnov1-1/+10
Regulator-vsd-3v3 is supplied via GEN_3V3 rail which is an output of an "always on" load switch supplied by 3V3_MAIN. GEN_3V3 is also used as vin-supply by a number of peripherals, so adding it also allows us to follow the schematic more closely. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org, Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: ls1028a: Update #clock-cells of dpclk nodeWen He1-2/+2
Update the property #clock-cells = <1> to #clock-cells = <0> of the dpclk, since the Display output pixel clock driver provides single clock output. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: lx2160a: add tmu device nodeYuantian Tang1-16/+92
Add the TMU (Thermal Monitoring Unit) device node to enable TMU feature. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28ARM: imx: Add serial number support for i.MX6/7 SoCsAnson Huang1-1/+37
i.MX6/7 SoCs have a 64-bit SoC unique ID stored in OCOTP, it can be used as SoC serial number, add this support for i.MX6Q/6DL/6SL/6SX/6SLL/6UL/6ULL/6ULZ/7D, see below example on i.MX6Q: root@imx6qpdlsolox:~# cat /sys/devices/soc0/serial_number 240F31D4E1FDFCA7 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mn: fix compatible string for sdmaShengjiu Wang1-3/+3
SDMA in i.MX8MN should use same configuration as i.MX8MQ So need to change compatible string to be "fsl,imx8mq-sdma". Fixes: 6c3debcbae47 ("arm64: dts: freescale: Add i.MX8MN dtsi support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28arm64: dts: imx8mm: fix compatible string for sdmaShengjiu Wang1-3/+3
SDMA in i.MX8MM should use same configuration as i.MX8MQ So need to change compatible string to be "fsl,imx8mq-sdma". Fixes: a05ea40eb384 ("arm64: dts: imx: Add i.mx8mm dtsi support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28ARM: dts: imx53-qsb: Use DRM bindings for the Seiko 43WVF1G panelFabio Estevam1-20/+24
Currently the parallel panel that is supported is the CLAA WVGA panel, which is the one that comes with the i.MX51 Babbage board. The default parallel panel that goes with the imx53-qsb board is the Seiko 43WVF1G LCD, so switch to the Seiko one. While at it convert to DRM bindings. The parallel display still remains disabled as the default display port is the TVE output. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28ARM: dts: imx53: Spelling s/configration/configuration/Geert Uytterhoeven1-1/+1
Fix misspelling of "configuration". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28perf/x86: Synchronize PMU task contexts on optimized context switchesAlexey Budankov1-0/+7
Install Intel specific PMU task context synchronization adapter and extend optimized context switch path with PMU specific task context synchronization to fix LBR callstack virtualization on context switches. Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Song Liu <songliubraving@fb.com> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: https://lkml.kernel.org/r/9c6445a9-bdba-ef03-3859-f1f91198f27a@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-10-28perf/x86/intel: Implement LBR callstack context synchronizationAlexey Budankov2-0/+26
Implement intel_pmu_lbr_swap_task_ctx() method updating counters of the events that requested LBR callstack data on a sample. The counter can be zero for the case when task context belongs to a thread that has just come from a block on a futex and the context contains saved (lbr_stack_state == LBR_VALID) LBR register values. For the values to be restored at LBR registers on the next thread's switch-in event it swaps the counter value with the one that is expected to be non zero at the previous equivalent task perf event context. Swap operation type ensures the previous task perf event context stays consistent with the amount of events that requested LBR callstack data on a sample. Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Song Liu <songliubraving@fb.com> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: https://lkml.kernel.org/r/261ac742-9022-c3f4-5885-1eae7415b091@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-10-28perf/x86: Install platform specific ->swap_task_ctx() adapterAlexey Budankov1-0/+8
Bridge perf core and x86 swap_task_ctx() method calls. Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Song Liu <songliubraving@fb.com> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: https://lkml.kernel.org/r/b157e97d-32c3-aeaf-13ba-47350c677906@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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