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2019-07-22x86/paravirt: Drop {read,write}_cr8() hooksAndrew Cooper8-66/+1
There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by lapic_{suspend,resume}(). Saving and restoring cr8 independently of the rest of the Local APIC state isn't a clever thing to be doing. Delete the suspend/resume cr8 handling, which shrinks the size of struct saved_context, and allows for the removal of both PVOPS. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Juergen Gross <jgross@suse.com> Link: https://lkml.kernel.org/r/20190715151641.29210-1-andrew.cooper3@citrix.com
2019-07-22x86/apic: Initialize TPR to block interrupts 16-31Andy Lutomirski1-2/+5
The APIC, per spec, is fundamentally confused and thinks that interrupt vectors 16-31 are valid. This makes no sense -- the CPU reserves vectors 0-31 for exceptions (faults, traps, etc). Obviously, no device should actually produce an interrupt with vector 16-31, but robustness can be improved by setting the APIC TPR class to 1, which will prevent delivery of an interrupt with a vector below 32. Note: This is *not* intended as a security measure against attackers who control malicious hardware. Any PCI or similar hardware that can be controlled by an attacker MUST be behind a functional IOMMU that remaps interrupts. The purpose of this change is to reduce the chance that a certain class of device malfunctions crashes the kernel in hard-to-debug ways. Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/dc04a9f8b234d7b0956a8d2560b8945bcd9c4bf7.1563117760.git.luto@kernel.org
2019-07-22ARM: dts: imx6ul: fix clock frequency property name of I2C busesSébastien Szymanski5-6/+6
A few boards set clock frequency of their I2C buses with "clock_frequency" property. The right property is "clock-frequency". Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: sunxi: Switch from phy to phy-handleMaxime Ripard41-41/+41
The phy device tree property has been deprecated in favor of phy-handle, let's replace it. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-22ARM: dts: sunxi: Switch to the generic PHY propertiesMaxime Ripard4-15/+14
The DWMAC specific properties to manage the PHY have been superseeded by the generic PHY properties. Let's move to it. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-22ARM: dts: opos6uldev: use OF graph to describe the displaySébastien Szymanski1-21/+16
To make use of the new eLCDIF DRM driver OF graph description is required. Describe the display using OF graph nodes. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: defconfig: Build imx8 ddr pmu as moduleLeonard Crestez1-0/+1
This is available on all imx8 but is not "boot critical" in any way so build as a module. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Frank Li <frank.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22powerpc/tm: Fix oops on sigreturn on systems without TMMichael Neuling2-0/+8
On systems like P9 powernv where we have no TM (or P8 booted with ppc_tm=off), userspace can construct a signal context which still has the MSR TS bits set. The kernel tries to restore this context which results in the following crash: Unexpected TM Bad Thing exception at c0000000000022fc (msr 0x8000000102a03031) tm_scratch=800000020280f033 Oops: Unrecoverable exception, sig: 6 [#1] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries Modules linked in: CPU: 0 PID: 1636 Comm: sigfuz Not tainted 5.2.0-11043-g0a8ad0ffa4 #69 NIP: c0000000000022fc LR: 00007fffb2d67e48 CTR: 0000000000000000 REGS: c00000003fffbd70 TRAP: 0700 Not tainted (5.2.0-11045-g7142b497d8) MSR: 8000000102a03031 <SF,VEC,VSX,FP,ME,IR,DR,LE,TM[E]> CR: 42004242 XER: 00000000 CFAR: c0000000000022e0 IRQMASK: 0 GPR00: 0000000000000072 00007fffb2b6e560 00007fffb2d87f00 0000000000000669 GPR04: 00007fffb2b6e728 0000000000000000 0000000000000000 00007fffb2b6f2a8 GPR08: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR12: 0000000000000000 00007fffb2b76900 0000000000000000 0000000000000000 GPR16: 00007fffb2370000 00007fffb2d84390 00007fffea3a15ac 000001000a250420 GPR20: 00007fffb2b6f260 0000000010001770 0000000000000000 0000000000000000 GPR24: 00007fffb2d843a0 00007fffea3a14a0 0000000000010000 0000000000800000 GPR28: 00007fffea3a14d8 00000000003d0f00 0000000000000000 00007fffb2b6e728 NIP [c0000000000022fc] rfi_flush_fallback+0x7c/0x80 LR [00007fffb2d67e48] 0x7fffb2d67e48 Call Trace: Instruction dump: e96a0220 e96a02a8 e96a0330 e96a03b8 394a0400 4200ffdc 7d2903a6 e92d0c00 e94d0c08 e96d0c10 e82d0c18 7db242a6 <4c000024> 7db243a6 7db142a6 f82d0c18 The problem is the signal code assumes TM is enabled when CONFIG_PPC_TRANSACTIONAL_MEM is enabled. This may not be the case as with P9 powernv or if `ppc_tm=off` is used on P8. This means any local user can crash the system. Fix the problem by returning a bad stack frame to the user if they try to set the MSR TS bits with sigreturn() on systems where TM is not supported. Found with sigfuz kernel selftest on P9. This fixes CVE-2019-13648. Fixes: 2b0a576d15e0 ("powerpc: Add new transactional memory state to the signal context") Cc: stable@vger.kernel.org # v3.9 Reported-by: Praveen Pandey <Praveen.Pandey@in.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190719050502.405-1-mikey@neuling.org
2019-07-21ARM: Delete netx a second timeLinus Walleij20-1860/+0
Commit ceb02dcf676f ARM: delete netx machine deleted the mach-netx machine. Then eight days later it was resurrected by SPDX tag fixes. I think. Taking the liberty to fix some additional debug uart cruft. Link: https://lore.kernel.org/r/20190721224157.6597-1-linus.walleij@linaro.org Fixes: ceb02dcf676f ("ARM: delete netx machine") Acked-By: Robert Schwebel <r.schwebel@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-22arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platformsAnson Huang1-0/+1
ARCH_MXC platforms needs system counter as broadcast timer to support cpuidle, enable it by default. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: defconfig: Select CONFIG_CLK_IMX8MN by defaultAnson Huang1-0/+1
Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: imx7ulp: Fix usb-phy unit address formatFabio Estevam1-1/+1
The following warning is seen when building with W=1: arch/arm/boot/dts/imx7ulp.dtsi:189.31-195.5: Warning (simple_bus_reg): /bus@40000000/usb-phy@0x40350000: simple-bus unit address format error, expected "40350000" Fix it as suggested by removing the extra "0x" notation. Fixes: 5b7bd456318a ("ARM: dts: imx7ulp: add imx7ulp USBOTG1 support") Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: dts: imx8mq-librem5: Enable MIPI D-PHYGuido Günther1-0/+4
This enables the Mixel MIPI D-PHY on the Librem 5 devkit Signed-off-by: Guido Günther <agx@sigxcpu.org> Acked-by: Angus Ainslie (Purism) <angus@akkea.ca> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: dts: imx8mq: Add MIPI D-PHYGuido Günther1-0/+13
Add a node for the Mixel MIPI D-PHY, "disabled" by default. Signed-off-by: Guido Günther <agx@sigxcpu.org> Acked-by: Angus Ainslie (Purism) <angus@akkea.ca> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: imx7ulp: add edma device nodeRobin Gong1-0/+28
Add edma device node in dts. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: imx7-colibri: Remove unneeded snvs_pwrkey nodeFabio Estevam1-4/+0
Since commit 4664179fe679 ("ARM: dts: imx7s: Enable SNVS power key according to board design") snvs_pwrkey is disabled by default, so there is no need for disabling it explicitly in the board dts anymore. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: imx7d-zii-rpu2: Remove unneeded snvs_pwrkey nodeFabio Estevam1-4/+0
Since commit 4664179fe679 ("ARM: dts: imx7s: Enable SNVS power key according to board design") snvs_pwrkey is disabled by default, so there is no need for disabling it explicitly in the board dts anymore. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: Add ZII support for ZII i.MX7 RMU2 boardAndrey Smirnov2-0/+358
Add support for ZII's i.MX7 based Remote Modem Unit 2 (RMU2) board. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Bob Langer <Bob.Langer@zii.aero> Cc: Liang Pan <Liang.Pan@zii.aero> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: imx6sll: correct sdma compatibleRobin Gong1-1/+1
Correct sdma compatible since ecspi errata ERR009165 has been fixed on i.mx6sll as i.mx6ul. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22ARM: dts: imx6ul: add dma support on ecspiRobin Gong1-0/+8
Add dma support on ecspi. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: defconfig: Select CONFIG_PINCTRL_IMX8MN by defaultAnson Huang1-0/+1
Enable CONFIG_PINCTRL_IMX8MN by default to support i.MX8MN pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: defconfig: Enable SDMA on i.mx8mq/8mmRobin Gong1-0/+3
Enable SDMA support on i.mx8mq/8mm chips, including enabling CONFIG_FW_LOADER_USER_HELPER/CONFIG_FW_LOADER_USER_HELPER_FALLBACK for firmware loaded by udev. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-22arm64: dts: rockchip: Specify override mode for kevin panelSean Paul1-0/+14
This patch adds an override mode for kevin devices. The mode increases both back porches to allow a pixel clock of 26666kHz as opposed to the 'typical' value of 252750kHz. This is needed to avoid interference with the touch digitizer on these laptops. Cc: Doug Anderson <dianders@chromium.org> Cc: Eric Anholt <eric@anholt.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Sean Paul <seanpaul@chromium.org> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-22ARM: dts: rockchip: Specify rk3288-veyron-minnie's display timingsDouglas Anderson1-0/+12
Just like we did for rk3288-veyron-chromebook, we want to be able to use one of the fixed PLLs in the system to make the pixel clock for minnie. Specifying these timings matches us with how the display is used on the downstream Chrome OS kernel. See https://crrev.com/c/323211. Unlike what we did for rk3288-veyron-chromebook, this CL actually changes the timings (though not the pixel clock) that is used when using the upstream kernel. Booting up a minnie shows that it ended up with a 66.67 MHz pixel clock but it was still using the porches/blankings it would have wanted for a 72.5 MHz pixel clock. NOTE: compared to the downstream kernel, this seems to cause a slightly different result reported in the 'modetest' command on a Chromebook. The downstream kernel shows: 1280x800 60 1280 1298 1330 1351 800 804 822 830 66667 With this patch we have: 1280x800 59 1280 1298 1330 1351 800 804 822 830 66666 Specifically modetest was reporting 60 Hz on the downstream kernel but the upstream kernel does the math and comesup with 59 (because we actually achieve 59.45 Hz). Also upstream doesn't round the Hz up when converting to kHz--it seems to truncate. ALSO NOTE: when I look at the EDID from the datasheet, I see: -hsync -vsync ...but it seems like we've never actually run with that so I've continued leaving that out. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-22ARM: dts: rockchip: Specify rk3288-veyron-chromebook's display timingsDouglas Anderson2-0/+16
Let's document the display timings that most veyron chromebooks (like jaq, jerry, mighty, speedy) have been using out in the field. This uses the standard blankings but a slightly slower clock rate, thus getting a refresh rate 58.3 Hz. NOTE: this won't really do anything except cause DRM to properly report the refresh rate since vop_crtc_mode_fixup() was rounding the pixel clock to 74.25 MHz anyway. Apparently the adjusted rate isn't exposed to userspace so it's important that the rate we're trying to achieve is mostly right. For the downstream kernel change related to this see See https://crrev.com/c/324558. NOTE: minnie uses a different panel will be fixed up in a future patch, so for now we'll just delete the panel timings there. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-21MIPS: pte_special()/pte_mkspecial() supportDmitry Korotin3-2/+20
Add support for pte_special() & pte_mkspecial(), replacing our previous stubs with functional implementations. Signed-off-by: Dmitry Korotin <dkorotin@wavecomp.com> [paul.burton@mips.com: - Fix for CONFIG_PHYS_ADDR_T_64BIT && CONFIG_CPU_MIPS32. - Rewrite commit message.] Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
2019-07-21MIPS: BMIPS: add clock controller nodesJonas Gorski6-15/+51
Now that we have a driver for the clock controller, add nodes to allow devices to make use of it. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org>
2019-07-21MIPS: DTS: jz4740: Add node for the MMC driverPaul Cercueil1-3/+18
Add a devicetree node for the jz4740-mmc driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mmc@vger.kernel.org
2019-07-21MIPS: Decode config3 register on Ingenic SoCsPaul Cercueil1-0/+8
XBurst misses a config2 register, so config3 decode was skipped in decode_configs(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21MIPS: Rename JZRISC to XBURSTPaul Cercueil6-9/+9
The real name of the CPU present in the JZ line of SoCs from Ingenic is XBurst, not JZRISC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> [paul.burton@mips.com: Leave /proc/cpuinfo string as-is.] Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21ARM: dts: at91: Avoid colliding 'display' node and property namesRob Herring4-4/+4
While properties and child nodes with the same name are valid DT, the practice is not encouraged. Furthermore, the collision is problematic for YAML encoded DT. Let's just avoid the issue and rename the nodes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20190516225614.1458-1-robh@kernel.org Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-07-21MIPS: Undefine PMD_ORDER for 32-bit buildsDaniel Silsby1-1/+1
During an update long ago to conform to 4-level page code, PMD_ORDER was changed from 0 to 1, despite the fact that a PMD table is not used at all in a 32-bit MIPS build. PMD_ORDER does not seem to be used in these builds. Now, it matches PUD_ORDER, a nonsense #define to give a build failure with informative error. The older commit that had redefined PMD_ORDER was commit c6e8b587718c ("Update MIPS to use the 4-level pagetable code thereby getting rid of the compacrapability headers.") Signed-off-by: Daniel Silsby <dansilsby@gmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21MIPS: ingenic: Add support for huge pagesDaniel Silsby1-0/+1
The Ingenic jz47xx SoC series of 32-bit MIPS CPUs support huge pages. Signed-off-by: Daniel Silsby <dansilsby@gmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21MIPS: Decouple CPU_SUPPORTS_HUGEPAGES from 64BITDaniel Silsby1-2/+2
We now have partial 32-bit MIPS huge page support, so there's no need to restrict these config options only to 64-bit systems. Signed-off-by: Daniel Silsby <dansilsby@gmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21MIPS: Add partial 32-bit huge page supportDaniel Silsby3-7/+73
This adds initial support for huge pages to 32-bit MIPS systems. Systems with extended addressing enabled (EVA,XPA,Alchemy/Netlogic) are not yet supported. With huge pages enabled, this implementation will increase page table memory overhead to match that of a 64-bit MIPS system. However, the cache-friendliness of page table walks is not affected significantly. Signed-off-by: Daniel Silsby <dansilsby@gmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21MIPS: Disallow CPU_SUPPORTS_HUGEPAGES for XPA,EVADaniel Silsby1-0/+1
In preparation for 32-bit MIPS huge page support. EVA,XPA are extended-addressing modes for 32-bit MIPS systems. Because huge pages aren't currently supported in 32-bit MIPS, this doesn't take any features away from EVA,XPA-enabled systems. However, the soon-to- come 32-bit MIPS huge page support doesn't yet support them. This also disables CPU_SUPPORTS_HUGEPAGES for the small number of 32-bit MIPS CPUs from Alchemy/Netlogic that support a custom 36-bit extended addressing. It's unknown if they even support huge pages in hardware. Signed-off-by: Daniel Silsby <dansilsby@gmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2019-07-21hexagon: switch to generic version of pte allocationMike Rapoport1-32/+2
The hexagon implementation pte_alloc_one(), pte_alloc_one_kernel(), pte_free_kernel() and pte_free() is identical to the generic except of lack of __GFP_ACCOUNT for the user PTEs allocation. Switch hexagon to use generic version of these functions. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-07-21parisc: Flush ITLB in flush_tlb_all_local() only on split TLB machinesHelge Deller1-1/+2
flush_tlb_all_local() flushes the ITLB and DTLB of the CPU. In case the machine does not have separate ITLBs and DTLBs, use the alternative functionality to replace the code which flushes the ITLB with nops while keeping the code which flushes the DTLB. Signed-off-by: Helge Deller <deller@gmx.de>
2019-07-21parisc: add kprobe_fault_handler()Sven Schnelle1-0/+4
Add kprobe_fault_handler() to fix compilation for PA-RISC. On PA-RISC we actually don't need that function as the recovery counter is restored after interrupt. See the PA-RISC 2.0 Architecture Manual, pg. 4-8, Figure 4-4: "Interruption Processing". Fixes: b98cca444d28 ("mm, kprobes: generalize and rename notify_page_fault() as kprobe_page_fault()") Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de>
2019-07-20Merge tag 'dma-mapping-5.3-1' of git://git.infradead.org/users/hch/dma-mappingLinus Torvalds4-1/+38
Pull dma-mapping fixes from Christoph Hellwig: "Fix various regressions: - force unencrypted dma-coherent buffers if encryption bit can't fit into the dma coherent mask (Tom Lendacky) - avoid limiting request size if swiotlb is not used (me) - fix swiotlb handling in dma_direct_sync_sg_for_cpu/device (Fugang Duan)" * tag 'dma-mapping-5.3-1' of git://git.infradead.org/users/hch/dma-mapping: dma-direct: correct the physical addr in dma_direct_sync_sg_for_cpu/device dma-direct: only limit the mapping size if swiotlb could be used dma-mapping: add a dma_addressing_limited helper dma-direct: Force unencrypted DMA under SME for certain DMA masks
2019-07-20Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds31-195/+218
Pull x86 fixes from Thomas Gleixner: "A set of x86 specific fixes and updates: - The CR2 corruption fixes which store CR2 early in the entry code and hand the stored address to the fault handlers. - Revert a forgotten leftover of the dropped FSGSBASE series. - Plug a memory leak in the boot code. - Make the Hyper-V assist functionality robust by zeroing the shadow page. - Remove a useless check for dead processes with LDT - Update paravirt and VMware maintainers entries. - A few cleanup patches addressing various compiler warnings" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/entry/64: Prevent clobbering of saved CR2 value x86/hyper-v: Zero out the VP ASSIST PAGE on allocation x86, boot: Remove multiple copy of static function sanitize_boot_params() x86/boot/compressed/64: Remove unused variable x86/boot/efi: Remove unused variables x86/mm, tracing: Fix CR2 corruption x86/entry/64: Update comments and sanity tests for create_gap x86/entry/64: Simplify idtentry a little x86/entry/32: Simplify common_exception x86/paravirt: Make read_cr2() CALLEE_SAVE MAINTAINERS: Update PARAVIRT_OPS_INTERFACE and VMWARE_HYPERVISOR_INTERFACE x86/process: Delete useless check for dead process with LDT x86: math-emu: Hide clang warnings for 16-bit overflow x86/e820: Use proper booleans instead of 0/1 x86/apic: Silence -Wtype-limits compiler warnings x86/mm: Free sme_early_buffer after init x86/boot: Fix memory leak in default_get_smp_config() Revert "x86/ptrace: Prevent ptrace from clearing the FS/GS selector" and fix the test
2019-07-20Merge branch 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds11-61/+87
Pull core fixes from Thomas Gleixner: - A collection of objtool fixes which address recent fallout partially exposed by newer toolchains, clang, BPF and general code changes. - Force USER_DS for user stack traces [ Note: the "objtool fixes" are not all to objtool itself, but for kernel code that triggers objtool warnings. Things like missing function size annotations, or code that confuses the unwinder etc. - Linus] * 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (27 commits) objtool: Support conditional retpolines objtool: Convert insn type to enum objtool: Fix seg fault on bad switch table entry objtool: Support repeated uses of the same C jump table objtool: Refactor jump table code objtool: Refactor sibling call detection logic objtool: Do frame pointer check before dead end check objtool: Change dead_end_function() to return boolean objtool: Warn on zero-length functions objtool: Refactor function alias logic objtool: Track original function across branches objtool: Add mcsafe_handle_tail() to the uaccess safe list bpf: Disable GCC -fgcse optimization for ___bpf_prog_run() x86/uaccess: Remove redundant CLACs in getuser/putuser error paths x86/uaccess: Don't leak AC flag into fentry from mcsafe_handle_tail() x86/uaccess: Remove ELF function annotation from copy_user_handle_tail() x86/head/64: Annotate start_cpu0() as non-callable x86/entry: Fix thunk function ELF sizes x86/kvm: Don't call kvm_spurious_fault() from .fixup x86/kvm: Replace vmx_vmenter()'s call to kvm_spurious_fault() with UD2 ...
2019-07-20Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-0/+3
Pull CONFIG_PREEMPT_RT stub config from Thomas Gleixner: "The real-time preemption patch set exists for almost 15 years now and while the vast majority of infrastructure and enhancements have found their way into the mainline kernel, the final integration of RT is still missing. Over the course of the last few years, we have worked on reducing the intrusivenness of the RT patches by refactoring kernel infrastructure to be more real-time friendly. Almost all of these changes were benefitial to the mainline kernel on their own, so there was no objection to integrate them. Though except for the still ongoing printk refactoring, the remaining changes which are required to make RT a first class mainline citizen are not longer arguable as immediately beneficial for the mainline kernel. Most of them are either reordering code flows or adding RT specific functionality. But this now has hit a wall and turned into a classic hen and egg problem: Maintainers are rightfully wary vs. these changes as they make only sense if the final integration of RT into the mainline kernel takes place. Adding CONFIG_PREEMPT_RT aims to solve this as a clear sign that RT will be fully integrated into the mainline kernel. The final integration of the missing bits and pieces will be of course done with the same careful approach as we have used in the past. While I'm aware that you are not entirely enthusiastic about that, I think that RT should receive the same treatment as any other widely used out of tree functionality, which we have accepted into mainline over the years. RT has become the de-facto standard real-time enhancement and is shipped by enterprise, embedded and community distros. It's in use throughout a wide range of industries: telecommunications, industrial automation, professional audio, medical devices, data acquisition, automotive - just to name a few major use cases. RT development is backed by a Linuxfoundation project which is supported by major stakeholders of this technology. The funding will continue over the actual inclusion into mainline to make sure that the functionality is neither introducing regressions, regressing itself, nor becomes subject to bitrot. There is also a lifely user community around RT as well, so contrary to the grim situation 5 years ago, it's a healthy project. As RT is still a good vehicle to exercise rarely used code paths and to detect hard to trigger issues, you could at least view it as a QA tool if nothing else" * 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/rt, Kconfig: Introduce CONFIG_PREEMPT_RT
2019-07-20Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds15-211/+198
Pull more KVM updates from Paolo Bonzini: "Mostly bugfixes, but also: - s390 support for KVM selftests - LAPIC timer offloading to housekeeping CPUs - Extend an s390 optimization for overcommitted hosts to all architectures - Debugging cleanups and improvements" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (25 commits) KVM: x86: Add fixed counters to PMU filter KVM: nVMX: do not use dangling shadow VMCS after guest reset KVM: VMX: dump VMCS on failed entry KVM: x86/vPMU: refine kvm_pmu err msg when event creation failed KVM: s390: Use kvm_vcpu_wake_up in kvm_s390_vcpu_wakeup KVM: Boost vCPUs that are delivering interrupts KVM: selftests: Remove superfluous define from vmx.c KVM: SVM: Fix detection of AMD Errata 1096 KVM: LAPIC: Inject timer interrupt via posted interrupt KVM: LAPIC: Make lapic timer unpinned KVM: x86/vPMU: reset pmc->counter to 0 for pmu fixed_counters KVM: nVMX: Ignore segment base for VMX memory operand when segment not FS or GS kvm: x86: ioapic and apic debug macros cleanup kvm: x86: some tsc debug cleanup kvm: vmx: fix coccinelle warnings x86: kvm: avoid constant-conversion warning x86: kvm: avoid -Wsometimes-uninitized warning KVM: x86: expose AVX512_BF16 feature to guest KVM: selftests: enable pgste option for the linker on s390 KVM: selftests: Move kvm_create_max_vcpus test to generic code ...
2019-07-20Merge tag 'kbuild-v5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuildLinus Torvalds5-11/+6
Pull more Kbuild updates from Masahiro Yamada: - match the directory structure of the linux-libc-dev package to that of Debian-based distributions - fix incorrect include/config/auto.conf generation when Kconfig creates it along with the .config file - remove misleading $(AS) from documents - clean up precious tag files by distclean instead of mrproper - add a new coccinelle patch for devm_platform_ioremap_resource migration - refactor module-related scripts to read modules.order instead of $(MODVERDIR)/*.mod files to get the list of created modules - remove MODVERDIR - update list of header compile-test - add -fcf-protection=none flag to avoid conflict with the retpoline flags when CONFIG_RETPOLINE=y - misc cleanups * tag 'kbuild-v5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (25 commits) kbuild: add -fcf-protection=none when using retpoline flags kbuild: update compile-test header list for v5.3-rc1 kbuild: split out *.mod out of {single,multi}-used-m rules kbuild: remove 'prepare1' target kbuild: remove the first line of *.mod files kbuild: create *.mod with full directory path and remove MODVERDIR kbuild: export_report: read modules.order instead of .tmp_versions/*.mod kbuild: modpost: read modules.order instead of $(MODVERDIR)/*.mod kbuild: modsign: read modules.order instead of $(MODVERDIR)/*.mod kbuild: modinst: read modules.order instead of $(MODVERDIR)/*.mod scsi: remove pointless $(MODVERDIR)/$(obj)/53c700.ver kbuild: remove duplication from modules.order in sub-directories kbuild: get rid of kernel/ prefix from in-tree modules.{order,builtin} kbuild: do not create empty modules.order in the prepare stage coccinelle: api: add devm_platform_ioremap_resource script kbuild: compile-test headers listed in header-test-m as well kbuild: remove unused hostcc-option kbuild: remove tag files by distclean instead of mrproper kbuild: add --hash-style= and --build-id unconditionally kbuild: get rid of misleading $(AS) from documents ...
2019-07-20x86/entry/64: Prevent clobbering of saved CR2 valueThomas Gleixner1-1/+10
The recent fix for CR2 corruption introduced a new way to reliably corrupt the saved CR2 value. CR2 is saved early in the entry code in RDX, which is the third argument to the fault handling functions. But it missed that between saving and invoking the fault handler enter_from_user_mode() can be called. RDX is a caller saved register so the invoked function can freely clobber it with the obvious consequences. The TRACE_IRQS_OFF call is safe as it calls through the thunk which preserves RDX, but TRACE_IRQS_OFF_DEBUG is not because it also calls into C-code outside of the thunk. Store CR2 in R12 instead which is a callee saved register and move R12 to RDX just before calling the fault handler. Fixes: a0d14b8909de ("x86/mm, tracing: Fix CR2 corruption") Reported-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1907201020540.1782@nanos.tec.linutronix.de
2019-07-20KVM: x86: Add fixed counters to PMU filterEric Hankland2-7/+25
Updates KVM_CAP_PMU_EVENT_FILTER so it can also whitelist or blacklist fixed counters. Signed-off-by: Eric Hankland <ehankland@google.com> [No need to check padding fields for zero. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-20KVM: nVMX: do not use dangling shadow VMCS after guest resetPaolo Bonzini1-1/+7
If a KVM guest is reset while running a nested guest, free_nested will disable the shadow VMCS execution control in the vmcs01. However, on the next KVM_RUN vmx_vcpu_run would nevertheless try to sync the VMCS12 to the shadow VMCS which has since been freed. This causes a vmptrld of a NULL pointer on my machime, but Jan reports the host to hang altogether. Let's see how much this trivial patch fixes. Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Cc: Liran Alon <liran.alon@oracle.com> Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-20KVM: VMX: dump VMCS on failed entryPaolo Bonzini1-0/+1
This is useful for debugging, and is ratelimited nowadays. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-07-20KVM: x86/vPMU: refine kvm_pmu err msg when event creation failedLike Xu1-2/+2
If a perf_event creation fails due to any reason of the host perf subsystem, it has no chance to log the corresponding event for guest which may cause abnormal sampling data in guest result. In debug mode, this message helps to understand the state of vPMC and we may not limit the number of occurrences but not in a spamming style. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Like Xu <like.xu@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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