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2018-11-29arm64: dts: meson: p230: disable advertisement EEE for GbE.He Yangxuan1-0/+1
This patch disable EEE advertisement for P230 board (DWMAC + RTL8211F). If not disable it, the network connection is not stable, will got issues like throughput drop or broken link. Signed-off-by: He Yangxuan <yangxuan8282@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-axg: enable SCPIJerome Brunet1-0/+26
Enable SCPI on the axg platform, with cpu clock and hwmon (core temperature) support Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-axg: correct sram shared mem unit-addressJerome Brunet1-2/+2
Correct the unit-address in the node name of the SRAM shared memory Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-axg: fix mailbox addressJerome Brunet1-2/+2
MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113. These mailboxes are needed for SCPI Fixes: 9d59b708500f ("arm64: dts: meson-axg: add initial A113D SoC DT support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-gx: Add hdmi_5v regulator as hdmi tx supplyNeil Armstrong5-0/+5
The hdmi_5v regulator must be enabled to provide power to the physical HDMI PHY and enables the HDMI 5V presence loopback for the monitor. Fixes: b409f625a6d5 ("ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-axg: add secure monitorJerome Brunet1-0/+4
Add the secure monitor device to the axg platform. With this, we can read the SoC serial number. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-axg: s400: add cts-rts to the bluetooth uartJerome Brunet1-1/+2
The uart used with bluetooth chipset on the s400 has flow control available. Let's enable it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-gxl-khadas-vim: fix GPIO lines namesNeil Armstrong1-2/+2
The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: 60795933b709 ("ARM64: dts: meson-gxl-khadas-vim: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-gxbb-odroidc2: fix GPIO lines namesNeil Armstrong1-2/+2
The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: b03c7d6438bb ("ARM64: dts: meson-gxbb-odroidc2: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-gxbb-nanopi-k2: fix GPIO lines namesNeil Armstrong1-2/+2
The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: 12ada0513d7a ("ARM64: dts: meson-gxbb-nanopi-k2: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-gxl-libretech-cc: fix GPIO lines namesNeil Armstrong1-2/+2
The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: 47884c5c746e ("ARM64: dts: meson-gxl-libretech-cc: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-axg: fix dtc warning about unit addressJerome Brunet2-16/+16
section 2.2.1 of the DT specs says: " If the node has no reg property, the @unit-address must be omitted and the node-name alone differentiates the node from other nodes at the same level in the tree" Simply replace the '@' with a '-' to fix this warning. Cc: Fabio Estevam <festevam@gmail.com> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson-gxl-s905x-khadas-vim enable BluetoothChristian Hewitt1-0/+7
This enables Bluetooth support for the following models: - Khadas VIM basic (AP6212) using firmware BCM43438A1.hcd - Khadas VIM pro (AP6255) using firmware BCM4345C0.hcd The AP6212 module used on the VIM basic has an ID clash with another device. To get Bluetooth working you either need to apply a kernel patch to drivers/bluetooth/btbcm.c so 0x2209 loads BCM43438A1 or the BCM43438A1.hcd firmware must be renamed to BCM43430A1.hcd. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29ARM: OMAP1: devices: configure omap1_spi100k only on OMAP7xxAaro Koskinen1-0/+3
Configure omap1_spi100k only on OMAP7xx. This allows running multiboard kernels on non-OMAP7xx HW with CONFIG_SPI_OMAP_100K enabled. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1/2: fix SoC name printingAaro Koskinen2-5/+5
Currently we get extra newlines on OMAP1/2 when the SoC name is printed: [ 0.000000] OMAP1510 [ 0.000000] revision 2 handled as 15xx id: bc058c9b93111a16 [ 0.000000] OMAP2420 [ 0.000000] Fix by using pr_cont. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1: ams-delta: Move AMS_DELTA_LATCH2_NGPIO to the board fileJanusz Krzysztofik2-4/+4
That symbol is not used outside the board file, there is no need to keep it in the board header. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1: ams-delta: Drop unused symbols from the board headerJanusz Krzysztofik1-4/+0
Those bitmap symbols defining pins of latch2 register, used with read()/write() calls before the latch was converted to a GPIO device, have been obsoleted by integer symbols defined inside the board file. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1: ams-delta: Drop board specific global GPIO numbersJanusz Krzysztofik2-19/+0
As all users of the board specific GPIO pins have been converted from legacy integer-based to descriptor-based interface, there is no longer a need to maintain statically assigned GPIO pin numbers. Drop support for that. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP: PM: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li1-12/+1
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1: clock: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li1-12/+2
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1: ams-delta: Provide GPIO lookup table for LED deviceJanusz Krzysztofik1-69/+26
Global GPIO numbers no longer have to be passed to leds-gpio driver, replace their assignment with a lookup table. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: OMAP1: ams-delta: make board header file local to mach-omap1Janusz Krzysztofik4-5/+4
Now as the board header file is no longer included by drivers, move it to the root directory of mach-omap1. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: dts: dra7: Move the ti,no-idle quirk on proper gmac nodeTero Kristo1-9/+8
Hwmod parses the DT hierarchically from root to search for matching ti,hwmod property. With the introduction of L4 data, we have two nodes with the ti,hwmod = "gmac" declaration, and the hwmod core only matches the first one found, which is the target-module one. This node incorrectly dropped the ti,no-idle flag, which causes number of problems, like ignoring errata i877, and also causing an intermittent boot failure on certain dra7 boards. Fix the issue by moving the ti,no-idle flag to the proper node. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29ARM: dts: Revert am335x mcasp ti-sysc changesTony Lindgren2-26/+31
Without this McASP FIFO would constantly underflow. EDMA test via dmatest works though. Let's revert the change for now until we know the root cause. Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-11-29Merge tag 's390-4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linuxLinus Torvalds2-0/+3
Pull s390 updates from Martin Schwidefsky: - Add two missing kfree calls on error paths in the vfio-ccw code - Make sure that all data structures of a mediated vfio-ccw device are initialized before registering it - Fix a sparse warning in vfio-ccw - A followup patch for the pgtable_bytes accounting, the page table downgrade for compat processes missed a mm_dec_nr_pmds() - Reject sampling requests in the PMU init function of the CPU measurement counter facility - With the vfio AP driver an AP queue needs to be reset on every device probe as the alternative driver could have modified the device state * tag 's390-4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390/mm: correct pgtable_bytes on page table downgrade s390/zcrypt: reinit ap queue state machine during device probe s390/cpum_cf: Reject request for sampling in event initialization s390/cio: Fix cleanup when unsupported IDA format is used s390/cio: Fix cleanup of pfn_array alloc failure vfio: ccw: Register mediated device once all structures are initialized s390/cio: make vfio_ccw_io_region static
2018-11-29Revert "xen/balloon: Mark unallocated host memory as UNUSABLE"Igor Druzhinin2-80/+4
This reverts commit b3cf8528bb21febb650a7ecbf080d0647be40b9f. That commit unintentionally broke Xen balloon memory hotplug with "hotplug_unpopulated" set to 1. As long as "System RAM" resource got assigned under a new "Unusable memory" resource in IO/Mem tree any attempt to online this memory would fail due to general kernel restrictions on having "System RAM" resources as 1st level only. The original issue that commit has tried to workaround fa564ad96366 ("x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f)") also got amended by the following 03a551734 ("x86/PCI: Move and shrink AMD 64-bit window to avoid conflict") which made the original fix to Xen ballooning unnecessary. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Juergen Gross <jgross@suse.com>
2018-11-29xen/x86: add diagnostic printout to xen_mc_flush() in case of errorJuergen Gross1-15/+20
Failure of an element of a Xen multicall is signalled via a WARN() only if the kernel is compiled with MC_DEBUG. It is impossible to know which element failed and why it did so. Change that by printing the related information even without MC_DEBUG, even if maybe in some limited form (e.g. without information which caller produced the failing element). Move the printing out of the switch statement in order to have the same information for a single call. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Juergen Gross <jgross@suse.com>
2018-11-29arm64: ftrace: Fix to enable syscall events on arm64Masami Hiramatsu1-0/+13
Since commit 4378a7d4be30 ("arm64: implement syscall wrappers") introduced "__arm64_" prefix to all syscall wrapper symbols in sys_call_table, syscall tracer can not find corresponding metadata from syscall name. In the result, we have no syscall ftrace events on arm64 kernel, and some bpf testcases are failed on arm64. To fix this issue, this introduces custom arch_syscall_match_sym_name() which skips first 8 bytes when comparing the syscall and symbol names. Fixes: 4378a7d4be30 ("arm64: implement syscall wrappers") Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-11-29arm64: Add workaround for Cortex-A76 erratum 1286807Catalin Marinas3-5/+44
On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual address for a cacheable mapping of a location is being accessed by a core while another core is remapping the virtual address to a new physical page using the recommended break-before-make sequence, then under very rare circumstances TLBI+DSB completes before a read using the translation being invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation and is shared with the Qualcomm Falkor erratum 1009 Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-11-29arm64: io: Ensure value passed to __iormb() is held in a 64-bit registerWill Deacon1-1/+2
As of commit 6460d3201471 ("arm64: io: Ensure calls to delay routines are ordered against prior readX()"), MMIO reads smaller than 64 bits fail to compile under clang because we end up mixing 32-bit and 64-bit register operands for the same data processing instruction: ./include/asm-generic/io.h:695:9: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths] return readb(addr); ^ ./arch/arm64/include/asm/io.h:147:58: note: expanded from macro 'readb' ^ ./include/asm-generic/io.h:695:9: note: use constraint modifier "w" ./arch/arm64/include/asm/io.h:147:50: note: expanded from macro 'readb' ^ ./arch/arm64/include/asm/io.h:118:24: note: expanded from macro '__iormb' asm volatile("eor %0, %1, %1\n" \ ^ Fix the build by casting the macro argument to 'unsigned long' when used as an input to the inline asm. Reported-by: Nick Desaulniers <nick.desaulniers@gmail.com> Reported-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-11-29ARM: tegra: Add VIC on Tegra124Thierry Reding1-0/+12
The Video Image Compositor can be used to perform a variety of image operations. Add a device tree node for it, so that it can be exposed as a host1x channel to userspace. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-29powerpc/msi: Fix NULL pointer access in teardown codeRadu Rendec1-1/+6
The arch_teardown_msi_irqs() function assumes that controller ops pointers were already checked in arch_setup_msi_irqs(), but this assumption is wrong: arch_teardown_msi_irqs() can be called even when arch_setup_msi_irqs() returns an error (-ENOSYS). This can happen in the following scenario: - msi_capability_init() calls pci_msi_setup_msi_irqs() - pci_msi_setup_msi_irqs() returns -ENOSYS - msi_capability_init() notices the error and calls free_msi_irqs() - free_msi_irqs() calls pci_msi_teardown_msi_irqs() This is easier to see when CONFIG_PCI_MSI_IRQ_DOMAIN is not set and pci_msi_setup_msi_irqs() and pci_msi_teardown_msi_irqs() are just aliases to arch_setup_msi_irqs() and arch_teardown_msi_irqs(). The call to free_msi_irqs() upon pci_msi_setup_msi_irqs() failure seems legit, as it does additional cleanup; e.g. list_del(&entry->list) and kfree(entry) inside free_msi_irqs() do happen (MSI descriptors are allocated before pci_msi_setup_msi_irqs() is called and need to be cleaned up if that fails). Fixes: 6b2fd7efeb88 ("PCI/MSI/PPC: Remove arch_msi_check_device()") Cc: stable@vger.kernel.org # v3.18+ Signed-off-by: Radu Rendec <radu.rendec@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-11-29ARM64: dts: hisilicon: Add all CPUs in cooling mapsViresh Kumar2-3/+16
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hi3660: Add missing cooling device properties for CPUsViresh Kumar1-0/+6
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: poplar: Standardize LED labels and triggersManivannan Sadhasivam1-6/+7
For all 96Boards, the following standard is used for onboard LEDs. green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power So lets adopt the same for Poplar, which is one of the 96Boards Enterprise edition platform. Due to absence of WLAN and BT support, corresponding LED nodes are not considered. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: hikey960: Standardize LED labels and triggersManivannan Sadhasivam1-9/+9
For all 96Boards, the following standard is used for onboard LEDs. green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power So lets adopt the same for HiKey960 which is one of the 96Boards CE platform. Since there is no trigger available for onboard-storage UFS now, user2 trigger is set to none. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: hikey: Standardize LED labels and triggersManivannan Sadhasivam1-12/+13
For all 96Boards, the following standard is used for onboard LEDs. green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power So lets adopt the same for HiKey, which is one of the 96Boards CE platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: hikey970: Add GPIO line namesManivannan Sadhasivam1-0/+317
Add GPIO line names for HiSilicon HiKey970 board based on HI3670 SoC. The Line names are derived from "hikey970-schematics.pdf" document and named in conjunction with 96Boards CE Specification v1.0. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: hikey970: Enable on-board UARTsManivannan Sadhasivam1-0/+20
Enable on-board UARTs on HiSilicon HiKey970 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: hi3670: Add UART nodesManivannan Sadhasivam2-0/+229
Add UART nodes for HiSilicon HI3670 SoC and also relevant pinmux/pinconf entries. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29arm64: dts: hisilicon: hi3670: Add GPIO controller supportManivannan Sadhasivam2-0/+380
Add GPIO controller support for HiSilicon HI3670 SoC based on ARM Primecell PL061 GPIO controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-11-29crypto: x86/chacha20 - Add a 4-block AVX-512VL variantMartin Willi2-0/+279
This version uses the same principle as the AVX2 version by scheduling the operations for two block pairs in parallel. It benefits from the AVX-512VL rotate instructions and the more efficient partial block handling using "vmovdqu8", resulting in a speedup of the raw block function of ~20%. Signed-off-by: Martin Willi <martin@strongswan.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-29crypto: x86/chacha20 - Add a 2-block AVX-512VL variantMartin Willi2-0/+178
This version uses the same principle as the AVX2 version. It benefits from the AVX-512VL rotate instructions and the more efficient partial block handling using "vmovdqu8", resulting in a speedup of ~20%. Unlike the AVX2 version, it is faster than the single block SSSE3 version to process a single block. Hence we engage that function for (partial) single block lengths as well. Signed-off-by: Martin Willi <martin@strongswan.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-29crypto: x86/chacha20 - Add a 8-block AVX-512VL variantMartin Willi3-0/+427
This variant is similar to the AVX2 version, but benefits from the AVX-512 rotate instructions and the additional registers, so it can operate without any data on the stack. It uses ymm registers only to avoid the massive core throttling on Skylake-X platforms. Nontheless does it bring a ~30% speed improvement compared to the AVX2 variant for random encryption lengths. The AVX2 version uses "rep movsb" for partial block XORing via the stack. With AVX-512, the new "vmovdqu8" can do this much more efficiently. The associated "kmov" instructions to work with dynamic masks is not part of the AVX-512VL instruction set, hence we depend on AVX-512BW as well. Given that the major AVX-512VL architectures provide AVX-512BW and this extension does not affect core clocking, this seems to be no problem at least for now. Signed-off-by: Martin Willi <martin@strongswan.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-29x86/resctrl: Remove unnecessary check for cbm_validate()Babu Moger1-1/+1
The Smatch static checker reports the following error after commit: a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the resource structure"): arch/x86/kernel/cpu/resctrl/ctrlmondata.c:227 parse_cbm() error: uninitialized symbol 'cbm_val'. arch/x86/kernel/cpu/resctrl/ctrlmondata.c:236 parse_cbm() error: uninitialized symbol 'cbm_val'. This could happen if ->cbm_validate() is NULL which could leave cbm_val uninitialized. However, there is no case where ->cbm_validate() can be NULL as it is initialized based on a vendor check. So it is either an Intel or an AMD version it points to. And in both the cases it is initialized properly. Thus, remove the first check. Verified the fix running Smatch. [ bp: massage commit message. ] Fixes: a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the resource structure") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Reinette Chatre <reinette.chatre@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20181128224234.22998-1-babu.moger@amd.com
2018-11-29ARM: defconfig: Enable the PL111 DRM driver on vexpressLinus Walleij1-4/+8
This updates the Versatile defconfig to use the new P111 DRM driver that is merged in the DRM subsystem. We deactivate the old CLCD driver and activate the Pl111 DRM driver and the SiI9022 HDMI bridge. We activate DMA memory allocation using CMA so that the special graphics memory for the on-board CLCD can be used. Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-29ARM: defconfig: Update the vexpress defconfigLinus Walleij1-12/+0
Update the Versatile Express defconfig to match the Kconfig changes in the kernel. Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-29ARM: dts: Modernize the Vexpress PL111 integrationLinus Walleij9-121/+150
The Versatile Express was submitted with the actual display bridges unconnected (but defined in the device tree) and mock "panels" encoded in the device tree node of the PL111 controller. This doesn't even remotely describe the actual Versatile Express hardware. Exploit the SiI9022 bridge by connecting the PL111 pads to it, making it use EDID or fallback values to drive the monitor. The also has to use the reserved memory through the CMA pool rather than by open coding a memory region and remapping it explicitly in the driver. To achieve this, a reserved-memory node must exist in the root of the device tree, so we need to pull that out of the motherboard .dtsi include files, and push it into each top-level device tree instead. We do the same manouver for all the Versatile Express boards, taking into account the different location of the video RAM depending on which chip select is used on each platform. This plays nicely with the new PL111 DRM driver and follows the standard ways of assigning bridges and memory pools for graphics. Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Cc: Robin Murphy <robin.murphy@arm.com> Tested-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-28Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller16-146/+303
Trivial conflict in net/core/filter.c, a locally computed 'sdif' is now an argument to the function. Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-28arm64: defconfig: Enable some qcom remoteproc configsBjorn Andersson1-0/+6
Enable remoteproc configs to boot the remoteprocs on QC chipsets. These are common configs and not specific to a specific SoC so should be enabled across the board. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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