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2018-09-13ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsiJohn Crispin1-34/+34
There are various places inside this dtsi file where 8 spaces where used for indenting instead of tabs. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix PCI rangeMathias Kresin1-1/+1
The PCI range is invalid and PCI attached devices doen't work. Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg valueChristian Lamparter1-1/+1
while compiling an ipq4019 target, dtc will complain: regulator@b089000 unit address format error, expected "2089000" The saw0 regulator reg value seems to be copied and pasted from qcom-ipq8064.dtsi. This patch fixes the reg value to match that of the unit address which in turn silences the warning. (There is no driver for qcom,saw2 right now. So this went unnoticed) Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq supportMatthew McClintock1-28/+26
This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanismMatthew McClintock1-8/+17
v1 was the incorrect choice here and sometimes the board would not come up properly. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for ALS / proximityBrian Masney2-0/+38
This patch adds device tree bindings for the tsl2772 ALS / proximity sensor for the LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for mpu6515Brian Masney2-0/+67
This patch adds device tree bindings for the mpu6515 to the LG Nexus 5 (hammerhead) phone. Confirmed that the gyroscope / accelerometer (mpu6515), magnetometer (ak8963), and temperature / pressure (bmp280) sensors are available on the phone. Interrupts are not working properly on the ak8963 magnetometer so they are currently not configured. The bmp280 retuns temperature/pressure measurement skipped errors but will reliably work if I run: echo 1 > in_pressure_oversampling_ratio echo 1 > in_temp_oversampling_ratio Signed-off-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Add led and gpio-button nodes to ipq8064 boardsSricharan R3-0/+87
Add the dt nodes for enabling the leds and gpio-buttons. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsiSricharan R3-80/+77
The nodes in ipq8064-ap148.dts currently are common with boards that we will add next. So move the common data to ipq8064-v.1.0.dtsi. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Add sdcc nodes for ipq8064Sricharan R1-0/+76
The relevant data for sdcc. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Add pcie nodes for ipq8064Sricharan R1-0/+182
Adding the pcie nodes and pins. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid valueFrank Rowand1-13/+13
Change the third field of the "interrupts" property from IRQ_TYPE_NONE to the correct value. I do not have hardware documentation for these devices, so I followed a mail list suggestion to copy the flag values from the same type of node in arch/arm64/boot/dts/qcom/msm8916.dtsi Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt flag NONEFrank Rowand1-8/+8
Cosmetic change of integer value "0" in the third field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGHFrank Rowand1-8/+8
Cosmetic change of integer value "4" in the third field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt flag EDGE RISINGFrank Rowand1-1/+1
Cosmetic change of integer value "1" in the third field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPIFrank Rowand1-27/+29
Cosmetic change of integer value "0" in the first field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_PPIFrank Rowand1-6/+6
Cosmetic change of integer value "1" in the first field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: msm8996: Transition smp2p and smd to mailboxBjorn Andersson1-9/+4
The smd and smp2p drivers now support accessing the APCS GLOBAL IPC register through the mailbox framework, so migrate the msm8996 dts to use this and remove the syscon based APCS node. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: defconfig: Enable Qualcomm QRTRBjorn Andersson1-0/+3
The QRTR packet family is used for a wide range of communication between services in Qualcomm platforms. Examples of services using this transport for communication are remoteproc management, modem control, positioning, power management and WiFi. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8998: Add pm8998 thermal zoneMatthias Kaehlcke1-0/+24
The thermal zone uses spmi-temp-alarm as sensor, the trip points correspond to the PMIC thermal stages 1 and 2. The critical trip point at 125°C disables the partial PMIC shutdown at stage 2. Without an IIO input the sensor only reports a limited number of temperatures: - 37°C for temperatures below 105°C - 107°C for temperatures >= 105°C and < 125°C - 127°C for temperatures >= 125°C (the numbers correspond to a stage 1 threshold of 105°C) Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8998: Add spmi-temp-alarm nodeMatthias Kaehlcke1-0/+7
This adds the spmi-temp-alarm node to pm8998 based on the examples in the bindings. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: sdm845: Add dispcc nodeMatthias Kaehlcke1-0/+9
This adds the display clock controller node to sdm845 based on the examples in the bindings. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845: Add adsp, cdsp and slpi smp2pBjorn Andersson1-0/+88
Add the SMP2P nodes for the remoteproc states for adsp, cdsp and slpi. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845-mtp: Add nodes for USBDouglas Anderson1-0/+61
Set the various nodes to "okay" and hook up the regulators. NOTE: For now the main USB port (the one that goes out the Type C connector) is forced to host. Eventually someone will need to get the Type C detection hooked up and get this all integrated with the PMI8998 PMIC. The reason for forcing to "host" in the meantime is that this will leave us with one "host" and one "peripheral" port. In order for host mode this to work, we assume that the bootloader left things configured enough for us. Apparently the magic for that is is to do these writes on pmi8998: - pm_comm_write_byte(2, 0x1153, 0x2C, 0); - pm_comm_write_byte(2, 0x1152, 0x07, 0); - pm_comm_write_byte(2, 0x1140, 0x00, 0); - pm_comm_write_byte(2, 0x1140, 0x01, 0); Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845-mtp: Add RPMh VRM/XOB regulatorsDouglas Anderson1-0/+321
Add regulator devices for PMIC regulators managed via VRM and XOB RPMh accelerators. A few notes here: - Regulators are added directly to the board file. While it's true that this will mean a bunch of copy/pasting for other boards that are very similar, this is probably the right call since boards could make changes to the way these regulators are hooked up and trying to find a way to avoid duplication will result in some confusing node overrides. - Regulators that are hooked up to supply pins on the SoC are given an alias matching the name of that pin (pin name comes from the Qualcomm SoC "device specification" doc). - Other regulator labels are based on the schematic. If there is more than one logical name on the schematic for the same rail the secondary names are also listed and should be referred to as appropriate. - Regulators all default to HPM mode w/ no ability to switch modes. Future patches can switch things to LPM and possibly add dynamic load switching if we have determined there's a benefit. This should only be done for rails where we'll actually be able to take advantage of the lower power modes so we don't need to churn with lots of patches adding regulator_set_load() calls to drivers. NOTE: This patch is loosely based on one originally shared to me by David Collins. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845: Add USB-related nodesManu Gautam1-0/+196
This adds nodes for USB and related PHYs. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> [dianders: reworked quite a bit] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: Add AOSS reset driver node for SDM845Sibi Sankar1-0/+7
This patch adds the node to support AOSS reset driver on SDM845 Signed-off-by: Sibi Sankar <sibis@codeaurora.org> [bjorn: Updated addresses to match the binding that was merged] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: msm8996: Drop modelNiklas Cassel1-2/+0
DTS board files should always specify model and compatible. All DTS board files that includes msm8996.dtsi already specifies model and compatible, and will thus override the model and compatible in msm8996.dtsi. Drop model from msm8916.dtsi, since it is only a source of confusion. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: msm8916: Drop model and compatibleNiklas Cassel1-3/+0
DTS board files should always specify model and compatible. All DTS board files that includes msm8916.dtsi already specifies model and compatible, and will thus override the model and compatible in msm8916.dtsi. Drop model and compatible from msm8916.dtsi, since they are only a source of confusion. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: db820c: Add qcom,apq8096 to compatible stringNiklas Cassel1-1/+1
Add qcom,apq8096 to compatible string. This compatible is defined in Documentation/devicetree/bindings/arm/qcom.txt and is needed for e.g. drivers/cpufreq/qcom-cpufreq-kryo.c to be probed correctly (and for drivers/cpufreq/cpufreq-dt-platdev.c to work properly). Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: Populate pm8998 with additional nodesBjorn Andersson1-0/+32
Add pon, coincell and rtc to the first pm8998 sid. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add smp2p nodesBjorn Andersson1-0/+64
Add the adsp, modem and slpi smp2p nodes to msm8998. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add the qfprom nodeBjorn Andersson1-0/+7
Add the QFPROM nvmem node to msm8998 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add firmware nodeBjorn Andersson1-0/+6
Add the firmware and scm nodes for msm8998 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add smem related nodesBjorn Andersson1-0/+49
Add reserve-memory nodes, tcsr-mutex nodes and the smem node. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add pmi8998 fileBjorn Andersson2-0/+43
Add new dtsi file for the PMI8998, with its gpios and include all three PMICs in the MSM8998 MTP dts. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add tsens and thermal-zonesBjorn Andersson2-0/+231
Add the two tsens instances and the thermal zones for CPUs, GPUs, battery and skin sensors. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add RPM and regulators for MTPBjorn Andersson2-0/+209
Add nodes for RPM communication for MSM8998 and the regulator nodes for the MTP. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: Add msm8998 SoC and MTP board supportJoonwoo Park4-0/+378
Add initial device tree support for the Qualcomm MSM8998 SoC and MTP8998 evaluation board. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Restructured, removed its node and moved to SPDX headers] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8998: Add adc nodeMatthias Kaehlcke1-1/+11
This adds the adc node to pm8998 based on the examples in the bindings. It also fixes the order of the included headers. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: apq8096-db820c: Add resin nodeVinod Koul1-0/+14
Resin is board specific, so add the resin node in apq8096-db820c dtsi Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: apq8016-sbc: Add resin nodeVinod Koul1-0/+14
Resin is board specific so add the resin node in apq8016-sbc dtsi Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8994: Add PON nodeVinod Koul1-0/+18
Add PON and pwrkey as child nodes for PON driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8916: Add PON nodeVinod Koul1-5/+13
Add PON and pwrkey as child nodes for PON device. Also add additional properties for pwrkey i.e., linux,code Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13Merge tag 'tags/bcm2835-dt-next-2018-09-09' into devicetree/nextFlorian Fainelli4-0/+154
This pull request brings in a board DT for the Raspberry Pi Compute Module 3, its I/O board and enables the Ethernet LEDs for the RPi 3B+. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13ARM: dts: NSP: Wire up switch interruptsFlorian Fainelli1-1/+30
The Switch Register Access Block (SRAB) has one interrupt for link state change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt and sleep timer interrupts for each management ports (5,7,8). Wire those up so we can utilize them to speed up link resolution. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13ARM: dts: NSP: Enable SFP on bcm958625hrFlorian Fainelli1-0/+26
Enable the SFP connected to port 5 of the switch and wire up all GPIOs to the SFP cage. Because of a hardware limitation of the i2c controller on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to work, we use the i2c-gpio interface instead, which does not have that limitation. This allows us to read the SFP module EEPROM, which would not be possible otherwise since it exceeds that size during a single read transfer. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
2018-09-13arm64: dts: meson: Switch simple-mfd and syscon orderNeil Armstrong2-4/+4
The order between "syscon" and "simple-mfd" is important because in these particular cases, the node needs to be first a "simple-mfd" to expose it's sub-nodes, and later on a "syscon" to permit other nodes to access this register space through the "syscon" mechanism. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-13net: dsa: Add Lantiq / Intel DSA driver for vrx200Hauke Mehrtens1-4/+4
This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC. This switch is integrated in the DSL SoC, this SoC uses a GSWIP version 2.1, there are other SoCs using different versions of this IP block, but this driver was only tested with the version found in the VRX200. Currently only the basic features are implemented which will forward all packages to the CPU and let the CPU do the forwarding. The hardware also support Layer 2 offloading which is not yet implemented in this driver. The GPHY FW loaded is now done by this driver and not any more by the separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver is a separate patch. to make use of the GPHY this switch driver is needed anyway. Other SoCs have more embedded GPHYs so this driver should support a variable number of GPHYs. After the firmware was loaded the GPHY can be probed on the MDIO bus and it behaves like an external GPHY, without the firmware it can not be probed on the MDIO bus. The clock names in the sysctrl.c file have to be changed because the clocks are now used by a different driver. This should be cleaned up and a real common clock driver should provide the clocks instead. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-09-13net: lantiq: Add Lantiq / Intel VRX200 Ethernet driverHauke Mehrtens1-3/+3
This drives the PMAC between the GSWIP Switch and the CPU in the VRX200 SoC. This is currently only the very basic version of the Ethernet driver. When the DMA channel is activated we receive some packets which were send to the SoC while it was still in U-Boot, these packets have the wrong header. Resetting the IP cores did not work so we read out the extra packets at the beginning and discard them. This also adapts the clock code in sysctrl.c to use the default name of the device node so that the driver gets the correct clock. sysctrl.c should be replaced with a proper common clock driver later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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