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2018-07-13x86/kvm: Allow runtime control of L1D flushThomas Gleixner2-6/+9
All mitigation modes can be switched at run time with a static key now: - Use sysfs_streq() instead of strcmp() to handle the trailing new line from sysfs writes correctly. - Make the static key management handle multiple invocations properly. - Set the module parameter file to RW Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.954525119@linutronix.de
2018-07-13x86/kvm: Serialize L1D flush parameter setterThomas Gleixner1-2/+6
Writes to the parameter files are not serialized at the sysfs core level, so local serialization is required. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.873642605@linutronix.de
2018-07-13x86/kvm: Add static key for flush alwaysThomas Gleixner1-5/+11
Avoid the conditional in the L1D flush control path. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.790914912@linutronix.de
2018-07-13x86/kvm: Move l1tf setup functionThomas Gleixner1-46/+77
In preparation of allowing run time control for L1D flushing, move the setup code to the module parameter handler. In case of pre module init parsing, just store the value and let vmx_init() do the actual setup after running kvm_init() so that enable_ept is having the correct state. During run-time invoke it directly from the parameter setter to prepare for run-time control. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.694063239@linutronix.de
2018-07-13x86/l1tf: Handle EPT disabled state properThomas Gleixner3-45/+54
If Extended Page Tables (EPT) are disabled or not supported, no L1D flushing is required. The setup function can just avoid setting up the L1D flush for the EPT=n case. Invoke it after the hardware setup has be done and enable_ept has the correct state and expose the EPT disabled state in the mitigation status as well. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.612160168@linutronix.de
2018-07-13x86/kvm: Drop L1TF MSR list approachThomas Gleixner1-36/+7
The VMX module parameter to control the L1D flush should become writeable. The MSR list is set up at VM init per guest VCPU, but the run time switching is based on a static key which is global. Toggling the MSR list at run time might be feasible, but for now drop this optimization and use the regular MSR write to make run-time switching possible. The default mitigation is the conditional flush anyway, so for extra paranoid setups this will add some small overhead, but the extra code executed is in the noise compared to the flush itself. Aside of that the EPT disabled case is not handled correctly at the moment and the MSR list magic is in the way for fixing that as well. If it's really providing a significant advantage, then this needs to be revisited after the code is correct and the control is writable. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.516940445@linutronix.de
2018-07-13x86/litf: Introduce vmx status variableThomas Gleixner3-13/+54
Store the effective mitigation of VMX in a status variable and use it to report the VMX state in the l1tf sysfs file. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lkml.kernel.org/r/20180713142322.433098358@linutronix.de
2018-07-13arm64: dts: stingray: add bcm958802a802x dtsVladimir Olovyannikov2-0/+28
Add bcm958802a802x dts to be used on all Stingray smart NIC PS225 board variants Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-07-13arm64: dts: stingray: add PAXC supportRay Jui2-0/+65
Add PAXC support to Broadcom Stingray SoC Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-07-13ARM: net: bpf: improve 64-bit ALU implementationRussell King1-5/+24
Improbe the 64-bit ALU implementation from: movw r8, #65532 movt r8, #65535 movw r9, #65535 movt r9, #65535 ldr r7, [fp, #-44] adds r7, r7, r8 str r7, [fp, #-44] ldr r7, [fp, #-40] adc r7, r7, r9 str r7, [fp, #-40] to: movw r8, #65532 movt r8, #65535 movw r9, #65535 movt r9, #65535 ldrd r6, [fp, #-44] adds r6, r6, r8 adc r7, r7, r9 strd r6, [fp, #-44] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-13ARM: net: bpf: improve 64-bit store implementationRussell King1-26/+26
Improve the 64-bit store implementation from: ldr r6, [fp, #-8] str r8, [r6] ldr r6, [fp, #-8] mov r7, #4 add r7, r6, r7 str r9, [r7] to: ldr r6, [fp, #-8] str r8, [r6] str r9, [r6, #4] We leave the store as two separate STR instructions rather than using STRD as the store may not be aligned, and STR can handle misalignment. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-13ARM: net: bpf: improve 64-bit sign-extended immediate loadRussell King1-4/+3
Improve the 64-bit sign-extended immediate from: mov r6, #1 str r6, [fp, #-52] ; 0xffffffcc mov r6, #0 str r6, [fp, #-48] ; 0xffffffd0 to: mov r6, #1 mov r7, #0 strd r6, [fp, #-52] ; 0xffffffcc Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-13ARM: net: bpf: improve 64-bit load immediate implementationRussell King1-12/+20
Rather than writing each 32-bit half of the 64-bit immediate value separately when the register is on the stack: movw r6, #45056 ; 0xb000 movt r6, #60979 ; 0xee33 str r6, [fp, #-44] ; 0xffffffd4 mov r6, #0 str r6, [fp, #-40] ; 0xffffffd8 arrange to use the double-word store when available instead: movw r6, #45056 ; 0xb000 movt r6, #60979 ; 0xee33 mov r7, #0 strd r6, [fp, #-44] ; 0xffffffd4 Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-13ARM: multi_v7_defconfig: enable STM32 DCMI media supportHugues Fruchet1-0/+1
Enables support of STM32 DCMI V4L2 media driver. Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: multi_v7_defconfig: enable STM32 DMAv2, DMAMUX and MDMAPierre-Yves MORDRET1-0/+3
This enables drivers for STM32: - DMAv2 - DMMAUX - MDMA Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: multi_v7_defconfig: enable STM32 RTCAmelie Delaunay1-0/+1
Enable the STM32 Real Time Clock (RTC) driver, implemented on STM32MP1 SoC. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: update iwdg with lsi clock name for stm32f429Ludovic Barre1-0/+1
This patch updates iwdg watchdog to use lsi clock name. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1Ludovic Barre1-0/+5
This patch activates independent watchdog support for stm32mp157c board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: add iwdg2 support for stm32mp157cLudovic Barre1-0/+8
This patch adds independent watchdog support for stm32mp157c. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: Reorder nodes in stm32mp157c-ed1Alexandre Torgue1-11/+11
Nodes should be ordered in alphabetic order. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: remove gpio aliases for stm32mp157cAlexandre Torgue1-14/+0
GPIO aliases are not used by stm32 pinctrl driver. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1Christophe Roullier2-0/+66
MAC is connected to a PHY in RGMII mode. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: Add ethernet dwmac on stm32mp1Christophe Roullier1-0/+30
Add Ethernet support (Synopsys MAC IP 4.20a) on stm32mp1 SOC. Enable feature supported by the stmmac driver, such as TSO. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: Add syscfg on stm32mp1Christophe Roullier1-0/+5
System configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: add SPI1 support on stm32mp157c-ev1Amelie Delaunay2-1/+21
This patch adds SPI1 support on stm32mp157c-ev1 board. SPI1 is available on GPIO expansion connector but kept disabled so these pins can be used as GPIOs by default. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: add SPI support on stm32mp157cAmelie Delaunay1-0/+84
This patch adds all SPI instances on stm32mp157c. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: Add DFSDM support to stm32mp157cFabrice Gasnier1-0/+70
stm32mp157c has DFSDM (Digital Filter For Sigma Delta Modulators) hardware with 6 filter instances. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: Add ADC support to stm32mp157cFabrice Gasnier1-0/+36
stm32mp157c has an ADC block with two physical ADCs. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: enable USB OTG HS on stm32mp157c-ev1Amelie Delaunay1-0/+7
This patch enables USB OTG HS on stm32mp157c-ev1 in Peripheral mode. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: add USB OTG HS support for stm32mp157c SoCAmelie Delaunay1-0/+15
This patch adds support for USB OTG HS on STM32MP157C SoC. USB OTG HS controller is based on DWC2 controller. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp157c-ev1Amelie Delaunay1-0/+6
This patch enables USB Host (USBH) EHCI controller on stm32mp157c-ev1. As a hub is used between USBH and USB connectors, no need to enable USBH OHCI controller: all low- and full-speed traffic is managed by the hub. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2018-07-13arm64: dts: marvell: armada-37xx: update the crypto engine compatibleAntoine Tenart1-1/+1
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they should be used whenever possible. This patch updates the Marvell Armada 37xx device tree accordingly. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-07-13arm64: dts: marvell: armada-cp110: update the crypto engine compatibleAntoine Tenart1-1/+1
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they should be used whenever possible. This patch updates the Marvell cp110 device tree accordingly. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-07-13KVM: s390: Fix storage attributes migration with memory slotsClaudio Imbrenda3-135/+195
This is a fix for several issues that were found in the original code for storage attributes migration. Now no bitmap is allocated to keep track of dirty storage attributes; the extra bits of the per-memslot bitmap that are always present anyway are now used for this purpose. The code has also been refactored a little to improve readability. Fixes: 190df4a212a ("KVM: s390: CMMA tracking, ESSA emulation, migration mode") Fixes: 4036e3874a1 ("KVM: s390: ioctls to get and set guest storage attributes") Acked-by: Janosch Frank <frankja@linux.vnet.ibm.com> Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1525106005-13931-3-git-send-email-imbrenda@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2018-07-13KVM: s390: Replace clear_user with kvm_clear_guestJanosch Frank1-1/+1
kvm_clear_guest also does the dirty tracking for us, which we want to have. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2018-07-13xen: setup pv irq ops vector earlierJuergen Gross2-16/+12
Setting pv_irq_ops for Xen PV domains should be done as early as possible in order to support e.g. very early printk() usage. The same applies to xen_vcpu_info_reset(0), as it is needed for the pv irq ops. Move the call of xen_setup_machphys_mapping() after initializing the pv functions as it contains a WARN_ON(), too. Remove the no longer necessary conditional in xen_init_irq_ops() from PVH V1 times to make clear this is a PV only function. Cc: <stable@vger.kernel.org> # 4.14 Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Juergen Gross <jgross@suse.com>
2018-07-12x86/intel_rdt: Fix possible circular lock dependencyReinette Chatre1-15/+14
Lockdep is reporting a possible circular locking dependency: ====================================================== WARNING: possible circular locking dependency detected 4.18.0-rc1-test-test+ #4 Not tainted ------------------------------------------------------ user_example/766 is trying to acquire lock: 0000000073479a0f (rdtgroup_mutex){+.+.}, at: pseudo_lock_dev_mmap but task is already holding lock: 000000001ef7a35b (&mm->mmap_sem){++++}, at: vm_mmap_pgoff+0x9f/0x which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #2 (&mm->mmap_sem){++++}: _copy_to_user+0x1e/0x70 filldir+0x91/0x100 dcache_readdir+0x54/0x160 iterate_dir+0x142/0x190 __x64_sys_getdents+0xb9/0x170 do_syscall_64+0x86/0x200 entry_SYSCALL_64_after_hwframe+0x49/0xbe -> #1 (&sb->s_type->i_mutex_key#3){++++}: start_creating+0x60/0x100 debugfs_create_dir+0xc/0xc0 rdtgroup_pseudo_lock_create+0x217/0x4d0 rdtgroup_schemata_write+0x313/0x3d0 kernfs_fop_write+0xf0/0x1a0 __vfs_write+0x36/0x190 vfs_write+0xb7/0x190 ksys_write+0x52/0xc0 do_syscall_64+0x86/0x200 entry_SYSCALL_64_after_hwframe+0x49/0xbe -> #0 (rdtgroup_mutex){+.+.}: __mutex_lock+0x80/0x9b0 pseudo_lock_dev_mmap+0x2f/0x170 mmap_region+0x3d6/0x610 do_mmap+0x387/0x580 vm_mmap_pgoff+0xcf/0x110 ksys_mmap_pgoff+0x170/0x1f0 do_syscall_64+0x86/0x200 entry_SYSCALL_64_after_hwframe+0x49/0xbe other info that might help us debug this: Chain exists of: rdtgroup_mutex --> &sb->s_type->i_mutex_key#3 --> &mm->mmap_sem Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&mm->mmap_sem); lock(&sb->s_type->i_mutex_key#3); lock(&mm->mmap_sem); lock(rdtgroup_mutex); *** DEADLOCK *** 1 lock held by user_example/766: #0: 000000001ef7a35b (&mm->mmap_sem){++++}, at: vm_mmap_pgoff+0x9f/0x110 rdtgroup_mutex is already being released temporarily during pseudo-lock region creation to prevent the potential deadlock between rdtgroup_mutex and mm->mmap_sem that is obtained during device_create(). Move the debugfs creation into this area to avoid the same circular dependency. Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: fenghua.yu@intel.com Cc: tony.luck@intel.com Cc: vikas.shivappa@linux.intel.com Cc: gavin.hindman@intel.com Cc: jithu.joseph@intel.com Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/fffb57f9c6b8285904c9a60cc91ce21591af17fe.1531332480.git.reinette.chatre@intel.com
2018-07-12ARM: net: bpf: use double-word load/stores where availableRussell King2-12/+45
Use double-word load and stores where support for this instruction is supported by the CPU architecture. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: always use odd/even register pairRussell King1-14/+14
Always use an odd/even register pair for our 64-bit registers, so that we're able to use the double-word load/store instructions in the future. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: avoid reloading 'array'Russell King1-5/+4
Rearranging the order of the initial tail call code a little allows is to avoid reloading the 'array' pointer. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: avoid reloading 'index'Russell King1-2/+3
Avoid reloading 'index' after we have validated it - it remains in tmp2[1] up to the point that we begin the code to index the pointer array, so with a little rearrangement of the registers, we can use the already loaded value. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: use ldr instructions with shifted rm registerRussell King2-2/+5
Rather than pre-shifting the rm register for the ldr in the tail call, shift it in the load instruction. This eliminates one unnecessary instruction. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: use immediate forms of instructions where possibleRussell King2-9/+13
Rather than moving constants to a register and then using them in a subsequent instruction, use them directly in the desired instruction cutting out the "middle" register. This removes two instructions from the tail call code path. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: imm12 constant conversionRussell King1-1/+49
Provide a version of the imm8m() function that the compiler can optimise when used with a constant expression. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: access eBPF scratch space using ARM FP registerRussell King1-19/+25
Access the eBPF scratch space using the frame pointer rather than our stack pointer, as the offsets from the ARM frame pointer are constant across all eBPF programs. Since we no longer reference the scratch space registers from the stack pointer, this simplifies emit_push_r64() as it no longer needs to know how many words are pushed onto the stack. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: 64-bit accessor functions for BPF registersRussell King1-113/+122
Provide a couple of 64-bit register accessors, and use them where appropriate Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: provide accessor functions for BPF registersRussell King1-201/+128
Many of the code paths need to have knowledge about whether a register is stacked or in a CPU register. Move this decision making to a pair of helper functions instead of having it scattered throughout the code. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: remove is_on_stack() and sstk/dstkRussell King1-176/+160
The decision about whether a BPF register is on the stack or in a CPU register is detected at the top BPF insn processing level, and then percolated throughout the remainder of the code. Since we now use negative register values to represent stacked registers, we can detect where a BPF register is stored without restoring to carrying this additional metadata through all code paths. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: use negative numbers for stacked registersRussell King1-98/+102
Use negative numbers for eBPF registers that live on the stack. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-07-12ARM: net: bpf: provide load/store ops with negative immediatesRussell King2-22/+41
Provide a set of load/store opcode generators that work with negative immediates as well as positive ones. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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