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2018-03-09perf/x86/intel: Properly save/restore the PMU state in the NMI handlerKan Liang1-1/+9
The PMU is disabled in intel_pmu_handle_irq(), but cpuc->enabled is not updated accordingly. This is fine in current usage because no-one checks it - but fix it for future code: for example, the drain_pebs() will be modified to fix an auto-reload bug. Properly save/restore the old PMU state. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: acme@kernel.org Cc: kernel test robot <fengguang.wu@intel.com> Link: http://lkml.kernel.org/r/6f44ee84-56f8-79f1-559b-08e371eaeb78@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-03-09perf/x86/intel: Fix large period handling on Broadwell CPUsKan Liang2-2/+2
Large fixed period values could be truncated on Broadwell, for example: perf record -e cycles -c 10000000000 Here the fixed period is 0x2540BE400, but the period which finally applied is 0x540BE400 - which is wrong. The reason is that x86_pmu::limit_period() uses an u32 parameter, so the high 32 bits of 'period' get truncated. This bug was introduced in: commit 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds") It's safe to use u64 instead of u32: - Although the 'left' is s64, the value of 'left' must be positive when calling limit_period(). - bdw_limit_period() only modifies the lowest 6 bits, it doesn't touch the higher 32 bits. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Fixes: 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds") Link: http://lkml.kernel.org/r/1519926894-3520-1-git-send-email-kan.liang@linux.intel.com [ Rewrote unacceptably bad changelog. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-03-09ARM: imx: Add basic msl support for imx6sllBai Ping6-4/+30
Add basic MSL support for i.MX6SLL. The i.MX 6SoloLiteLite application processors are NXP's latest additions to a growing family of multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX 6SoloLiteLite processors feature NXP's advanced implementation of the ARM Cortex-A9 core, which can be interfaced with LPDDR3 and LPDDR2 DRAM memory devices. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-08arm64: defconfig: enable more cpufreq governorsAmit Kucheria1-0/+8
Enable the various CPUFREQ governors and statistics to ease development. Don't change the default governor - performance governor. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: defconfig: enable thermal sensor on QCOM platformsAmit Kucheria1-0/+2
Enable the driver for the TSENS IP that is present across several QCOM SoCs. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: defconfig: Enable the APCS IPC driver on Qualcomm platformsAmit Kucheria1-0/+1
The APCS block is present on several Qualcomm SoCs e.g. 8916, 8996. On the 8916 it is needed to enable the clock controller that in turn enables cpufreq on the platform while on the 8996 it is needed for communication with RPM. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: qcom: Fix SPI5 config on MSM8996Ilia Lin1-2/+2
Set correct clocks and interrupt values. Fixes the incorrect SPI master configuration. This is mandatory to make the SPI5 interface functional. Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: msm8916: Add cpu cooling mapsRajendra Nayak1-0/+19
Add cpu cooling maps for cpu passive trip points. The cpu cooling device states are mapped to cpufreq based scaling frequencies. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: msm8996: Add rmtfs sharedmem nodeBjorn Andersson1-0/+11
A 2MB shared memory region is used on MSM8996 for exchanging sector data in rmtfs. Add this chunk of reserved memory now that we have the rmtfs-mem compatible to describe it and its memory protection properties. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: qcom: msm8916: Add CPU frequency scaling supportGeorgi Djakov1-0/+26
Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: qcom: msm8916: Add clock properties to the APCS nodeGeorgi Djakov1-0/+2
There are clock controller registers in the APCS block, which purpose is to control the main CPU mux and divider. Add the clock properties as part of the APCS device-tree node. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: qcom: msm8916: Probe the APCS mailbox driverGeorgi Djakov1-3/+4
The APCS block was exposed until now as a syscon, but now we have a proper driver for this block. Add the compatible string of the new driver to probe and register the mailbox functionality. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: qcom: msm8916: Add msm8916 A53 PLL DT nodeGeorgi Djakov1-0/+6
Add a device tree node for the A53 PLL, which exists on msm8916 platforms. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08arm64: dts: msm8996: Fix wrong use of GIC_CPU_MASK_SIMPLE()Rajendra Nayak1-4/+4
GICv3 does not have affinity bitmap in the binding for PPI interrupts. It can be specified using a 4th cell if needed as documented in the bindings. Clean up the wrong use of the affinity bitmap using the GIC_CPU_MASK_SIMPLE() macro Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08ARM: dts: add XOADC and IIO HWMON to APQ8064Linus Walleij1-0/+63
This adds the PM8921 XOADC node to the PM8921 PMIC node, defines the channels and further also define an IIO HWMON node for the channels that are used for housekeeping of voltages and die temperature for the PMIC chip die. Tested on the Nexus 7 tablet: lsiio Device 000: PM8921-XOADC cd /sys/bus/iio/devices/iio:device0 cat in_voltage10_input 616461 (0.625V reference voltage) cat in_voltage11_input (1.25V reference voltage) cat temp1_input 35852 (die temperature) Cc: John Stultz <john.stultz@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08ARM: dts: use 'atmel' as at24 manufacturer for qcom-apq8064-cm-qs600Bartosz Golaszewski1-1/+1
Using compatible strings without the <manufacturer> part for at24 is now deprecated. Use a correct 'atmel,<model>' value. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08ARM: dts: qcom: Add initial DTS file for Samsung Galaxy S5 phoneDaniele Debernardi2-0/+25
This DTS has support for the Samsung Galaxy S5 (codenamed klte). Initial version have support just for serial console. Cc: Andy Gross <andy.gross@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Daniele Debernardi <drebrez@gmail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-08Merge tag 'mips_fixes_4.16_4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mipsLinus Torvalds4-4/+14
Pull MIPS fixes from James Hogan: "A miscellaneous pile of MIPS fixes for 4.16: - move put_compat_sigset() to evade hardened usercopy warnings (4.16) - select ARCH_HAVE_PC_{SERIO,PARPORT} for Loongson64 platforms (4.16) - fix kzalloc() failure handling in ath25 (3.19) and Octeon (4.0) - fix disabling of IPIs during BMIPS suspend (3.19)" * tag 'mips_fixes_4.16_4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: MIPS: BMIPS: Do not mask IPIs during suspend MIPS: Loongson64: Select ARCH_MIGHT_HAVE_PC_SERIO MIPS: Loongson64: Select ARCH_MIGHT_HAVE_PC_PARPORT signals: Move put_compat_sigset to compat.h to silence hardened usercopy MIPS: OCTEON: irq: Check for null return on kzalloc allocation MIPS: ath25: Check for kzalloc allocation failure
2018-03-08arm64: defconfig: Enable NVIDIA Tegra194 supportMikko Perttunen1-0/+1
Enable NVIDIA Tegra194 support in the default 64-bit ARM configuration. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08KVM: nVMX: Enforce NMI controls on vmentry of L2 guestsKrish Sadhukhan1-2/+27
According to Intel SDM 26.2.1.1, the following rules should be enforced on vmentry: * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" VM-execution control must be 0. * If the “virtual NMIs” VM-execution control is 0, the “NMI-window exiting” VM-execution control must be 0. This patch enforces these rules when entering an L2 guest. Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Reviewed-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Jim Mattson <jmattson@google.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2018-03-08Merge branch 'dtc-update' into dt/nextRob Herring161-993/+1457
2018-03-08ARM: tegra: apalis-tk1: Support v1.2 hardware revisionMarcel Ziswiler3-0/+2303
Support the V1.2 hardware revision with the following pin muxing changes: Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 are now used as DDC pins. Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are now used as USB power enable signals. Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power enable signals are now used as GPIO3 and GPIO4. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Copyright period, spurious newlinesMarcel Ziswiler2-14/+3
Update the copyright period and get rid of some spurious newlines. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Hog group for ethernet, PCIe, reset GPIOsMarcel Ziswiler2-0/+28
The Apalis TK1 module uses some dedicated GPIOs as I210 gigabit Ethernet controller reset and to control RESET_MOCI aka reset module output carrier input on MXM3 pin 26. The Apalis Evaluation Board furthermore uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Add missing as3722 gpio0 configurationMarcel Ziswiler1-3/+3
As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Activate PWM pin muxing for pwm3Marcel Ziswiler1-4/+4
Activate PWM pin muxing for Apalis PWM3. Note that the same PWM3 is already active on pu6 being Apalis BKL1_PWM as well. Therefore exporting that one for raw sysfs access will fail and one has to revert to using the PWM backlight. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Set critical tripsMarcel Ziswiler1-24/+3
Set "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones. These trips can trigger shut down or reset. Similar to commit 40823f8e267f ("arm: tegra: set critical trips for Tegra124"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis/colibri: Remove unneeded reg propertyMarcel Ziswiler2-2/+0
As described in Documentation/devicetree/bindings/input/touchscreen/stmpe.txt there is no 'reg' property under stmpe_touchscreen, so remove it to fix the following build warning with W=1: arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (unit_address_vs_reg): Node /i2c@7000d000/stmpe811@41/stmpe_touchscreen has a reg or ranges property, but no unit name Similar to commit 89277e8e2679 ("ARM: dts: imx6qdl-apalis: Remove unneeded reg property"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis/colibri: Use correct compatible for RTCMarcel Ziswiler3-3/+3
All Toradex Carrier Boards use a st,m41t0 compatible RTC. Compared to a st,m41t00 this RTC has also an oscillator fail bit which allows to detect when the RTC lost track of time. Similar to commit c53bec16b150 ("ARM: dts: colibri/apalis: use correct compatible for RTC") covering our NXP i.MX and Vybrid based modules. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Fix I2C bus frequencies on Apalis/ColibriMarcel Ziswiler7-13/+18
Use a faster speed of 400 kbit/s for regular I2C busses. Use a slower speed of 10 kbit/s for DDC/EDID to improve reliability. Use a slower speed of 100 kbit/s for power I2C to be within specs of the LM95245 temperature sensor. While at it further annotate I2C pin usage. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: venice2: Remove duplicate pcie-1 nodeMarcel Ziswiler1-5/+0
Get rid of duplicate pcie-1 node. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: beaver: Remove invalid uses of rsvd1Marcel Ziswiler1-15/+15
Remove invalid uses of rsvd1 from Beaver device tree. Replace by actual function names of pinmux option 1. Taken from https://github.com/NVIDIA/tegra-pinmux-scripts commit b0aceda108c0 ("remove invalid uses of rsvd1 from beaver config"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Use proper IRQ type definitionsMarcel Ziswiler6-8/+8
This switches a few interrupt definitions that were using either GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW as IRQ type, which is invalid. This is mostly a cosmetic change, that doesn't affect any driver. Analogous to Paul's commit 38333641b6dd ("ARM: tegra: nyan: Use proper IRQ type definitions"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08x86/MCE: Cleanup and complete struct mce fields definitionsBorislav Petkov1-24/+28
The struct is part of the uapi, document that fact and all fields properly and fix formatting. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20180306142143.19990-3-bp@alien8.de
2018-03-08Merge branch 'ras/urgent' into ras/coreThomas Gleixner191-958/+1848
Pick up urgent fixes to apply further development changes.
2018-03-08x86/MCE: Serialize sysfs changesSeunghun Han1-1/+21
The check_interval file in /sys/devices/system/machinecheck/machinecheck<cpu number> directory is a global timer value for MCE polling. If it is changed by one CPU, mce_restart() broadcasts the event to other CPUs to delete and restart the MCE polling timer and __mcheck_cpu_init_timer() reinitializes the mce_timer variable. If more than one CPU writes a specific value to the check_interval file concurrently, mce_timer is not protected from such concurrent accesses and all kinds of explosions happen. Since only root can write to those sysfs variables, the issue is not a big deal security-wise. However, concurrent writes to these configuration variables is void of reason so the proper thing to do is to serialize the access with a mutex. Boris: - Make store_int_with_restart() use device_store_ulong() to filter out negative intervals - Limit min interval to 1 second - Correct locking - Massage commit message Signed-off-by: Seunghun Han <kkamagui@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/20180302202706.9434-1-kkamagui@gmail.com
2018-03-08x86/MCE: Save microcode revision in machine check recordsTony Luck2-1/+4
Updating microcode used to be relatively rare. Now that it has become more common we should save the microcode version in a machine check record to make sure that those people looking at the error have this important information bundled with the rest of the logged information. [ Borislav: Simplify a bit. ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Yazen Ghannam <yazen.ghannam@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/20180301233449.24311-1-tony.luck@intel.com
2018-03-08ARM: tegra: Fix ULPI regression on Tegra20Marcel Ziswiler1-1/+1
Since commit f8f8f1d04494 ("clk: Don't touch hardware when reparenting during registration") ULPI has been broken on Tegra20 leading to the following error message during boot: [ 1.974698] ulpi_phy_power_on: ulpi write failed [ 1.979384] tegra-ehci c5004000.usb: Failed to power on the phy [ 1.985434] tegra-ehci: probe of c5004000.usb failed with error -110 Debugging through the changes and finally also consulting the TRM revealed that rather than the CDEV2 clock off OSC requiring such pin muxing actually the PLL_P_OUT4 clock is in use. It looks like so far it just worked by chance of that one having been enabled which Stephen's commit now changed when reparenting sclk away from pll_p_out4 leaving that one disabled. Fix this by properly assigning the PLL_P_OUT4 clock as the ULPI PHY clock. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Add unit address to VDE IRAM areaThierry Reding1-1/+1
Add the missing unit address for the VDE IRAM area node in accordance with the mmio-sram device tree binding. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Add video decoder node on Tegra30Dmitry Osipenko1-0/+27
Add device tree node for the Video Decoder Engine found on Tegra30 SoC's. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Add IRAM node on Tegra30Dmitry Osipenko1-0/+8
IRAM is a static RAM that consists of four contiguous 64 KiB blocks, it is currently used to store CPU resume code, utilized by the video decoder engine and could be used as a general-purpose fast memory. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08arm64/kernel: kaslr: reduce module randomization range to 4 GBArd Biesheuvel3-15/+19
We currently have to rely on the GCC large code model for KASLR for two distinct but related reasons: - if we enable full randomization, modules will be loaded very far away from the core kernel, where they are out of range for ADRP instructions, - even without full randomization, the fact that the 128 MB module region is now no longer fully reserved for kernel modules means that there is a very low likelihood that the normal bottom-up allocation of other vmalloc regions may collide, and use up the range for other things. Large model code is suboptimal, given that each symbol reference involves a literal load that goes through the D-cache, reducing cache utilization. But more importantly, literals are not instructions but part of .text nonetheless, and hence mapped with executable permissions. So let's get rid of our dependency on the large model for KASLR, by: - reducing the full randomization range to 4 GB, thereby ensuring that ADRP references between modules and the kernel are always in range, - reduce the spillover range to 4 GB as well, so that we fallback to a region that is still guaranteed to be in range - move the randomization window of the core kernel to the middle of the VMALLOC space Note that KASAN always uses the module region outside of the vmalloc space, so keep the kernel close to that if KASAN is enabled. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-03-08arm64: module: don't BUG when exceeding preallocated PLT countArd Biesheuvel2-1/+4
When PLTs are emitted at relocation time, we really should not exceed the number that we counted when parsing the relocation tables, and so currently, we BUG() on this condition. However, even though this is a clear bug in this particular piece of code, we can easily recover by failing to load the module. So instead, return 0 from module_emit_plt_entry() if this condition occurs, which is not a valid kernel address, and can hence serve as a flag value that makes the relocation routine bail out. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-03-08arm64: tegra: Add device tree for the Tegra194 P2972-0000 boardMikko Perttunen3-0/+265
Add device tree files for the Tegra194 P2972-0000 development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08arm64: tegra: Add Tegra194 chip device treeMikko Perttunen1-0/+344
Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08x86/pti: Fix a comment typoSeunghun Han1-1/+1
s/visinble/visible/ Signed-off-by: Seunghun Han <kkamagui@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/1520397135-132809-1-git-send-email-kkamagui@gmail.com
2018-03-08x86/jailhouse: Allow to use PCI_MMCONFIG without ACPIJan Kiszka3-3/+7
Jailhouse does not use ACPI, but it does support MMCONFIG. Make sure the latter can be built without having to enable ACPI as well. Primarily, its required to make the AMD mmconf-fam10h_64 depend upon MMCONFIG and ACPI, instead of just the former. Saves some bytes in the Jailhouse non-root kernel. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: jailhouse-dev@googlegroups.com Cc: linux-pci@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Link: https://lkml.kernel.org/r/788bbd5325d1922235e9562c213057425fbc548c.1520408357.git.jan.kiszka@siemens.com
2018-03-08x86: Consolidate PCI_MMCONFIG configsJan Kiszka1-7/+4
Since e279b6c1d329 ("x86: start unification of arch/x86/Kconfig.*"), there exist two PCI_MMCONFIG entries, one from the original i386 and another from x86_64. Consolidate both entries into a single one. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: jailhouse-dev@googlegroups.com Cc: linux-pci@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Link: https://lkml.kernel.org/r/2a0ccd51ea6f7996e07162918228e23bdc1fbb03.1520408357.git.jan.kiszka@siemens.com
2018-03-08x86: Align x86_64 PCI_MMCONFIG with 32-bit variantJan Kiszka1-1/+2
Allow to enable PCI_MMCONFIG when only SFI is present and make this option default on. This will help consolidating both into one Kconfig statement. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: jailhouse-dev@googlegroups.com Cc: linux-pci@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Link: https://lkml.kernel.org/r/a2faf78c54f340f5549149e8b679c95950dae83d.1520408357.git.jan.kiszka@siemens.com
2018-03-08x86/jailhouse: Enable PCI mmconfig access in inmatesOtavio Pontes3-2/+12
Use the PCI mmconfig base address exported by jailhouse in boot parameters in order to access the memory mapped PCI configuration space. [Jan: rebased, fixed !CONFIG_PCI_MMCONFIG, used pcibios_last_bus] Signed-off-by: Otavio Pontes <otavio.pontes@intel.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: jailhouse-dev@googlegroups.com Cc: linux-pci@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: Bjorn Helgaas <bhelgaas@google.com> Link: https://lkml.kernel.org/r/2ee9e4401fa22377b3965893a558120f169be82b.1520408357.git.jan.kiszka@siemens.com
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