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2022-04-12ARM: dts: qcom: sdx65: Add spmi nodeRohit Agarwal1-0/+19
Add SPMI node to SDX65 dtsi. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1647411447-25249-2-git-send-email-quic_rohiagar@quicinc.com
2022-04-12arm64: dts: qcom: sc7280: Support gpu speedbinAkhil P Oommen1-0/+46
Add speedbin fuse and additional OPPs for gpu to support sc7280 SKUs. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226005021.v2.5.I4c2cb95f06f0c37038c80cc1ad20563fdf0618e2@changeid
2022-04-12ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064Ansuel Smith1-3/+5
Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com
2022-04-12ARM: dts: qcom: Add support for ASUS ZenWatch 2Luca Weiss3-0/+304
Add support for this smartwatch, based on Snapdragon 400 SoC. Currently supported functionality: * Internal storage * USB * Charger * Power button * Vibration motor * Bluetooth * Wifi Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226101939.1011551-2-luca@z3ntu.xyz
2022-04-12arm64: dts: qcom: ipq8074: fix the sleep clock frequencyKathiravan T1-1/+1
Sleep clock frequency should be 32768Hz. Lets fix it. Cc: stable@vger.kernel.org Fixes: 41dac73e243d ("arm64: dts: Add ipq8074 SoC and HK01 board support") Link: https://lore.kernel.org/all/e2a447f8-6024-0369-f698-2027b6edcf9e@codeaurora.org/ Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644581655-11568-1-git-send-email-quic_kathirav@quicinc.com
2022-04-12ARM: dts: qcom: msm8974: Drop flags for mdss irqsDmitry Baryshkov1-2/+2
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Fixes: 5a9fc531f6ec ("ARM: dts: msm8974: add display support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302225411.2456001-6-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8250: Drop flags for mdss irqsDmitry Baryshkov1-3/+3
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302225411.2456001-5-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sdm845: Drop flags for mdss irqsDmitry Baryshkov1-3/+3
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302225411.2456001-4-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sdm660: Drop flags for mdss irqsDmitry Baryshkov1-1/+1
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: ab290284398d ("arm64: dts: qcom: sdm660: Add required nodes for DSI1") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302225411.2456001-3-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sdm630: Drop flags for mdss irqsDmitry Baryshkov1-2/+2
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: b52555d590d1 ("arm64: dts: qcom: sdm630: Add MDSS nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302225411.2456001-2-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: msm8996: Drop flags for mdss irqsDmitry Baryshkov1-3/+3
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 12d540375736 ("arm64: dts: qcom: msm8996: Add DSI0 nodes") Fixes: 3a4547c1fc2f ("arm64: qcom: msm8996.dtsi: Add Display nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302225411.2456001-1-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450-hdk: add pcie nodesDmitry Baryshkov1-0/+21
Add device tree nodes for PCIe0/PCIe1 controllers and corresponding PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-8-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450-qrd: enable PCIe0 hostDmitry Baryshkov1-0/+4
Enable PCIe0 host on SM8450 QRD device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-7-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY deviceDmitry Baryshkov1-0/+6
Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-6-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450: add PCIe1 root deviceDmitry Baryshkov1-0/+96
Add device tree node for the second PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-5-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450: add PCIe1 PHY nodeDmitry Baryshkov1-0/+38
Add device tree node for the second PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-4-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450: add PCIe0 RC deviceDmitry Baryshkov1-0/+98
Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-3-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: sm8450: add PCIe0 PHY nodeDmitry Baryshkov1-2/+40
Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-2-dmitry.baryshkov@linaro.org
2022-04-13ARM: dts: aspeed: Add video engine to g6Howard Chiu1-0/+10
This node was accidentally removed by commit 645afe73f951 ("ARM: dts: aspeed: ast2600: Update XDMA engine node"). Fixes: 645afe73f951 ("ARM: dts: aspeed: ast2600: Update XDMA engine node") Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com> Link: https://lore.kernel.org/r/SG2PR06MB2315C57600A0132FEF40F21EE61E9@SG2PR06MB2315.apcprd06.prod.outlook.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-04-13ARM: dts: aspeed: romed8hm3: Fix GPIOB0 nameZev Weiss1-1/+1
This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a correction from ASRock Rack its name now reflects its actual functionality (POST_COMPLETE_N). Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC") Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220331022425.28606-2-zev@bewilderbeest.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-04-13ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor valuesZev Weiss1-0/+2
With this property set the sensor readings from these devices can now be calibrated properly. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC") Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220331022425.28606-1-zev@bewilderbeest.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-04-13ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin groupJae Hyun Yoo1-2/+2
Fix incorrect function mappings in pinctrl_qspi1_default and pinctrl_qspi2_default since their function should be SPI1 and SPI2 respectively. Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes") Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-8-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-04-13ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsiJohnny Huang1-0/+5
Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0#, FWSPICK, FWSPIMOSI and FWSPIMISO. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-7-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-04-13ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsiJae Hyun Yoo1-5/+0
FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl dtsi. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Fixes: 2f6edb6bcb2f ("ARM: dts: aspeed: Fix AST2600 quad spi group") Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-2-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-04-12ARM: dts: qcom: sdx65: Add support for APCS blockRohit Agarwal1-0/+9
The APCS block on SDX65 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com
2022-04-12ARM: dts: qcom: sdx65: Add support for A7 PLL clockRohit Agarwal1-0/+8
On SDX65 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
2022-04-12ARM: dts: qcom: pm8226: Add VADC nodeRayyan Ansari1-0/+34
Add a node for the voltage ADC (VADC) found in PM8226. Signed-off-by: Rayyan Ansari <rayyan@ansari.sh> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220209163841.7360-1-rayyan@ansari.sh
2022-04-12arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllersTaniya Das1-0/+43
Add the low pass audio clock controller device nodes. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202053207.14256-1-tdas@codeaurora.org
2022-04-12ARM: dts: qcom: ipq8064: User generic node name for DMAKuldeep Singh1-2/+2
Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410175056.79330-6-singh.kuldeep87k@gmail.com
2022-04-12ARM: dts: qcom: ipq4019: User generic node name for DMAKuldeep Singh5-9/+9
Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410175056.79330-5-singh.kuldeep87k@gmail.com
2022-04-12arm64: dts: qcom: msm8996: User generic node name for DMAKuldeep Singh1-1/+1
Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410175056.79330-4-singh.kuldeep87k@gmail.com
2022-04-12Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds17-107/+159
Pull kvm fixes from Paolo Bonzini: "x86: - Miscellaneous bugfixes - A small cleanup for the new workqueue code - Documentation syntax fix RISC-V: - Remove hgatp zeroing in kvm_arch_vcpu_put() - Fix alignment of the guest_hang() in KVM selftest - Fix PTE A and D bits in KVM selftest - Missing #include in vcpu_fp.c ARM: - Some PSCI fixes after introducing PSCIv1.1 and SYSTEM_RESET2 - Fix the MMU write-lock not being taken on THP split - Fix mixed-width VM handling - Fix potential UAF when debugfs registration fails - Various selftest updates for all of the above" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (24 commits) KVM: x86: hyper-v: Avoid writing to TSC page without an active vCPU KVM: SVM: Do not activate AVIC for SEV-enabled guest Documentation: KVM: Add SPDX-License-Identifier tag selftests: kvm: add tsc_scaling_sync to .gitignore RISC-V: KVM: include missing hwcap.h into vcpu_fp KVM: selftests: riscv: Fix alignment of the guest_hang() function KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put() selftests: KVM: Free the GIC FD when cleaning up in arch_timer selftests: KVM: Don't leak GIC FD across dirty log test iterations KVM: Don't create VM debugfs files outside of the VM directory KVM: selftests: get-reg-list: Add KVM_REG_ARM_FW_REG(3) KVM: avoid NULL pointer dereference in kvm_dirty_ring_push KVM: arm64: selftests: Introduce vcpu_width_config KVM: arm64: mixed-width check should be skipped for uninitialized vCPUs KVM: arm64: vgic: Remove unnecessary type castings KVM: arm64: Don't split hugepages outside of MMU write lock KVM: arm64: Drop unneeded minor version check from PSCI v1.x handler KVM: arm64: Actually prevent SMC64 SYSTEM_RESET2 from AArch32 KVM: arm64: Generally disallow SMC64 for AArch32 guests ...
2022-04-12stat: fix inconsistency between struct stat and struct compat_statMikulas Patocka1-4/+2
struct stat (defined in arch/x86/include/uapi/asm/stat.h) has 32-bit st_dev and st_rdev; struct compat_stat (defined in arch/x86/include/asm/compat.h) has 16-bit st_dev and st_rdev followed by a 16-bit padding. This patch fixes struct compat_stat to match struct stat. [ Historical note: the old x86 'struct stat' did have that 16-bit field that the compat layer had kept around, but it was changes back in 2003 by "struct stat - support larger dev_t": https://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git/commit/?id=e95b2065677fe32512a597a79db94b77b90c968d and back in those days, the x86_64 port was still new, and separate from the i386 code, and had already picked up the old version with a 16-bit st_dev field ] Note that we can't change compat_dev_t because it is used by compat_loop_info. Also, if the st_dev and st_rdev values are 32-bit, we don't have to use old_valid_dev to test if the value fits into them. This fixes -EOVERFLOW on filesystems that are on NVMe because NVMe uses the major number 259. Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Cc: Andreas Schwab <schwab@linux-m68k.org> Cc: Matthew Wilcox <willy@infradead.org> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2022-04-12arm64: defconfig: Enable Qualcomm GPI DMA DriverVinod Koul1-0/+1
Qualcomm GPI DMA Driver is used for DMA transfers for Serial engines like Geni I2C and SPI. Enable this dma driver Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220225044033.1376769-1-vkoul@kernel.org
2022-04-12arm64: dts: qcom: msm8916-huawei-g7: Add sound cardStephan Gerhold1-0/+46
The huawei-g7 uses the msm8916-wcd-digital/analog audio codecs similar to apq8016-sbc, so we can mostly copy paste it from there to make audio work correctly. The main difference is the hphl-jack-type-normally-open property, which is needed to avoid inverted audio jack detection. Note that at least on my device the jack detection is not fully reliable: sometimes headphones are detected as headsets (with microphone). However, this is not a big problem for typical usage. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410195113.13646-3-stephan@gerhold.net
2022-04-12arm64: dts: qcom: msm8916-huawei-g7: Clarify installation instructionsStephan Gerhold1-9/+4
The comment with installation instructions in the huawei-g7 device tree is a bit misleading and does not describe the recommended installation steps very well. The bootloader is actually not patched; to avoid all trouble with the vendor bootloader it is easier to bypass it completely by jumping to a custom bootloader (e.g. based on the open-source LK released by Qualcomm). To avoid confusion, simplify the comment to state only the problem and then refer to the wiki article which contains detailed suggested installation instructions. This will also make it easier to keep it up to date with new developments in the future. Fixes: 55056b229189 ("arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410195113.13646-2-stephan@gerhold.net
2022-04-12ARM: dts: qcom: apq8064: User generic node name for DMAKuldeep Singh1-3/+3
Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410175056.79330-2-singh.kuldeep87k@gmail.com
2022-04-12ARM: dts: qcom: mdm9615: User generic node name for DMAKuldeep Singh1-2/+2
Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410175056.79330-3-singh.kuldeep87k@gmail.com
2022-04-12arm64: dts: qcom: sm8250-edo: Add dual CS35L41 ampsKonrad Dybcio1-1/+29
Add nodes for dual Cirrus Logic CS35L41 audio amps connected via I2C. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222014806.22446-1-konrad.dybcio@somainline.org
2022-04-12arm64: dts: qcom: sc7280: Add reset entries for SDCC controllersShaik Sajida Bhanu1-0/+4
Add gcc hardware reset entries for eMMC and SD card. Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1649759528-15125-3-git-send-email-quic_c_sbhanu@quicinc.com
2022-04-12arm64: dts: qcom: sc7280-herobrine: Audio codec wants 1.8V, not 1.62VDouglas Anderson1-1/+14
The L2C rail on herobrine boards is intended to go to the audio codec. Let's override the 1.62V specified in the qcard.dtsi file to be 1.8V. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411141332.v2.1.I9f06fec63b978699fe62591fec9e5ac31bb3a69d@changeid
2022-04-12arm64: dts: qcom: ipq6018: Fix qmp usb3 phy nodeBhupesh Sharma1-2/+2
Fix the following 'make dtbs_check' warning(s) by using phy@ instead of lanes@ and by moving '#clock-cells' to sub-node: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: ssphy@78000: 'lane@78200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> [bjorn: s/clock-names/clock-cells/ per Shawn's feedback] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.org
2022-04-12arm64: dts: qcom: sm8450: Fix qmp ufs phy node (use phy@ instead of lanes@)Bhupesh Sharma1-1/+1
Fix the 'make dtbs_check' warning: arch/arm64/boot/dts/qcom/sm8450-qrd.dt.yaml: phy@1d87000: 'lanes@1d87400' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220228123019.382037-6-bhupesh.sharma@linaro.org
2022-04-12arm64: dts: qcom: sc7280: Fix qmp phy node (use phy@ instead of lanes@)Bhupesh Sharma1-1/+1
Fix the 'make dtbs_check' warning: arch/arm64/boot/dts/qcom/sc7280-idp.dt.yaml: phy@1c0e000: 'lanes@1c0e200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220228123019.382037-5-bhupesh.sharma@linaro.org
2022-04-12arm64: dts: qcom: msm8996-xiaomi: Drop max-microamp and vddp-ref-clk properties from QMP PHYBhupesh Sharma1-5/+0
The following properties are not supported and causing dtbs_check warnings. - vdda-phy-max-microamp - vdda-pll-max-microamp - vddp-ref-clk-max-microamp - vddp-ref-clk-always-on arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dt.yaml: phy@627000: 'vdda-phy-max-microamp', 'vddp-ref-clk-always-on', 'vddp-ref-clk-max-microamp' do not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Drop them from QMP PHY nodes for 'msm8996-xiaomi' dts. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220228123019.382037-4-bhupesh.sharma@linaro.org
2022-04-12arm64: dts: qcom: msm8916: Add BAM-DMUX for WWAN network interfacesStephan Gerhold1-0/+30
The BAM Data Multiplexer provides access to the network data channels of modems integrated into many older Qualcomm SoCs, including MSM8916. Add the nodes for the BAM DMA engine and BAM-DMUX to enable using WWAN on smartphones/tablets based on MSM8916. This should work out of the box with open-source WWAN userspace such as ModemManager. The nodes are disabled by default to avoid loading unnecessary drivers on devices that cannot use BAM-DMUX (e.g. DragonBoard 410c). However, strictly speaking the nodes could be enabled by default since both the bam_dma and bam_dmux driver will simply do nothing if the modem does not announce any BAM-DMUX channels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220228225400.146555-3-stephan@gerhold.net
2022-04-12arm64: dts: qcom: add pm8450 supportDmitry Baryshkov1-0/+59
Add PM8450 PMIC device tree include file. It is going to be used by SM8450-based devices. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226205035.1826360-8-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: pmr735a: stop depending on thermal_zones labelDmitry Baryshkov1-15/+17
Most of SoC device trees do not provide the thermal_zones label. Thus stop depending on it and use the full path to the thermal zones nodes. Fixes: 7a3544e5d4e8 ("arm64: dts: qcom: pmr735a: Add temp-alarm support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226205035.1826360-6-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: pm8350c: stop depending on thermal_zones labelDmitry Baryshkov1-15/+17
Most of SoC device trees do not provide the thermal_zones label. Thus stop depending on it and use the full path to the thermal zones nodes. Fixes: 3795fe7d497b ("arm64: dts: qcom: pm8350c: Add temp-alarm support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226205035.1826360-5-dmitry.baryshkov@linaro.org
2022-04-12arm64: dts: qcom: pmr735b: add temp sensor and thermal zone configDmitry Baryshkov1-0/+31
Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226205035.1826360-4-dmitry.baryshkov@linaro.org
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