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2022-04-09ARM: dts: s5pv210: align DMA channels with dtschemaKrzysztof Kozlowski2-7/+7
dtschema expects DMA channels in specific order (tx, rx and tx-sec). The order actually should not matter because dma-names is used however let's make it aligned with dtschema to suppress warnings like: i2s@eee30000: dma-names: ['rx', 'tx', 'tx-sec'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Co-developed-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/CY4PR04MB056779A9C50DC95987C5272ACB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-09ARM: dts: s5pv210: Adjust DMA node names to match specJonathan Bakker1-3/+3
DMA node names should be dma-controller according to the DT spec, so rename them from pdma/mdma. Prevents warnings when running make dtbs_check Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/CY4PR04MB0567F52ABAE0A3CCD3C7CE59CB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-09ARM: dts: s5pv210: Adjust memory reg entries to match specJonathan Bakker3-8/+7
The reg property of memory nodes should have pairs of offset, size; not all memory banks lumped in as one. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/CY4PR04MB05677849A13F41BF603906DFCB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-09ARM: dts: s5pv210: Correct interrupt name for bluetooth in AriesJonathan Bakker1-1/+1
Correct the name of the bluetooth interrupt from host-wake to host-wakeup. Fixes: 1c65b6184441b ("ARM: dts: s5pv210: Correct BCM4329 bluetooth node") Cc: <stable@vger.kernel.org> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/CY4PR04MB0567495CFCBDC8D408D44199CB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-09ARM: dts: s5pv210: Remove spi-cs-high on panel in AriesJonathan Bakker1-1/+0
Since commit 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors"), the panel has been blank due to an inverted CS GPIO. In order to correct this, drop the spi-cs-high from the panel SPI device. Fixes: 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors") Cc: <stable@vger.kernel.org> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/CY4PR04MB05670C771062570E911AF3B4CB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-09arm64: dts: rockchip: Change io-domains of bpi-r2-proFrank Wunderlich1-2/+2
New 1.0 Hardware revision has different io domain settings than the first board. Pre-1.0 version was not sold, so the setting can be savely overridden. Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220402110045.104031-2-linux@fw-web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-04-09RISC-V: KVM: include missing hwcap.h into vcpu_fpHeiko Stuebner1-0/+1
vcpu_fp uses the riscv_isa_extension mechanism which gets defined in hwcap.h but doesn't include that head file. While it seems to work in most cases, in certain conditions this can lead to build failures like ../arch/riscv/kvm/vcpu_fp.c: In function ‘kvm_riscv_vcpu_fp_reset’: ../arch/riscv/kvm/vcpu_fp.c:22:13: error: implicit declaration of function ‘riscv_isa_extension_available’ [-Werror=implicit-function-declaration] 22 | if (riscv_isa_extension_available(&isa, f) || | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../arch/riscv/kvm/vcpu_fp.c:22:49: error: ‘f’ undeclared (first use in this function) 22 | if (riscv_isa_extension_available(&isa, f) || Fix this by simply including the necessary header. Fixes: 0a86512dc113 ("RISC-V: KVM: Factor-out FP virtualization into separate sources") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-09RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put()Anup Patel1-2/+0
We might have RISC-V systems (such as QEMU) where VMID is not part of the TLB entry tag so these systems will have to flush all TLB entries upon any change in hgatp.VMID. Currently, we zero-out hgatp CSR in kvm_arch_vcpu_put() and we re-program hgatp CSR in kvm_arch_vcpu_load(). For above described systems, this will flush all TLB entries whenever VCPU exits to user-space hence reducing performance. This patch fixes above described performance issue by not clearing hgatp CSR in kvm_arch_vcpu_put(). Fixes: 34bde9d8b9e6 ("RISC-V: KVM: Implement VCPU world-switch") Cc: stable@vger.kernel.org Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-09arm64: dts: imx8qm: Correct SCU clock controller's compatible propertyLiu Ying1-1/+1
The fsl,scu.txt dt-binding documentation explicitly mentions that the compatible string should be either "fsl,imx8qm-clock" or "fsl,imx8qxp-clock", followed by "fsl,scu-clk". Also, i.MX8qm SCU clocks and i.MX8qxp SCU clocks are really not the same, so we have to set the compatible property according to SoC name. Let's correct the i.MX8qm clock controller's compatible property from "fsl,imx8qxp-clk", "fsl,scu-clk" to "fsl,imx8qm-clk", "fsl,scu-clk" . Fixes: f2180be18a63 ("arm64: dts: imx: add imx8qm common dts file") Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-09ARM: dts: imx7s: fix iomuxc_lpsr node nameAlexander Stein1-1/+1
Schema requires the node being named 'pinctrl'. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: dts: qcom: sa8155: Enable PCIe nodesBhupesh Sharma1-0/+15
SA8155p ADP board supports the PCIe0 controller in the RC mode (only). So add the support for the same. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220326055754.1796146-3-bhupesh.sharma@linaro.org
2022-04-08arm64: dts: qcom: sm8150: Add PCIe nodesBhupesh Sharma1-0/+243
Add nodes for the two PCIe controllers found on the SM8150 SoC. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220326055754.1796146-2-bhupesh.sharma@linaro.org
2022-04-08arm64: dts: qcom: sm8150: Add ufs power-domain entriesBhupesh Sharma1-0/+2
Add power-domain entries for UFS phy node in sm8150 dts. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> [bjorn: Dropped power-domain-names] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220323203052.1124683-1-bhupesh.sharma@linaro.org
2022-04-08arm64: dts: qcom: sm8150: Add pdc interrupt controller nodeBhupesh Sharma1-0/+10
Add pdc interrupt controller for sm8150. Cc: Maulik Shah <quic_mkshah@quicinc.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226184028.111566-4-bhupesh.sharma@linaro.org
2022-04-08Merge https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-nextJakub Kicinski4-33/+315
Daniel Borkmann says: ==================== pull-request: bpf-next 2022-04-09 We've added 63 non-merge commits during the last 9 day(s) which contain a total of 68 files changed, 4852 insertions(+), 619 deletions(-). The main changes are: 1) Add libbpf support for USDT (User Statically-Defined Tracing) probes. USDTs are an abstraction built on top of uprobes, critical for tracing and BPF, and widely used in production applications, from Andrii Nakryiko. 2) While Andrii was adding support for x86{-64}-specific logic of parsing USDT argument specification, Ilya followed-up with USDT support for s390 architecture, from Ilya Leoshkevich. 3) Support name-based attaching for uprobe BPF programs in libbpf. The format supported is `u[ret]probe/binary_path:[raw_offset|function[+offset]]`, e.g. attaching to libc malloc can be done in BPF via SEC("uprobe/libc.so.6:malloc") now, from Alan Maguire. 4) Various load/store optimizations for the arm64 JIT to shrink the image size by using arm64 str/ldr immediate instructions. Also enable pointer authentication to verify return address for JITed code, from Xu Kuohai. 5) BPF verifier fixes for write access checks to helper functions, e.g. rd-only memory from bpf_*_cpu_ptr() must not be passed to helpers that write into passed buffers, from Kumar Kartikeya Dwivedi. 6) Fix overly excessive stack map allocation for its base map structure and buckets which slipped-in from cleanups during the rlimit accounting removal back then, from Yuntao Wang. 7) Extend the unstable CT lookup helpers for XDP and tc/BPF to report netfilter connection tracking tuple direction, from Lorenzo Bianconi. 8) Improve bpftool dump to show BPF program/link type names, Milan Landaverde. 9) Minor cleanups all over the place from various others. * https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next: (63 commits) bpf: Fix excessive memory allocation in stack_map_alloc() selftests/bpf: Fix return value checks in perf_event_stackmap test selftests/bpf: Add CO-RE relos into linked_funcs selftests libbpf: Use weak hidden modifier for USDT BPF-side API functions libbpf: Don't error out on CO-RE relos for overriden weak subprogs samples, bpf: Move routes monitor in xdp_router_ipv4 in a dedicated thread libbpf: Allow WEAK and GLOBAL bindings during BTF fixup libbpf: Use strlcpy() in path resolution fallback logic libbpf: Add s390-specific USDT arg spec parsing logic libbpf: Make BPF-side of USDT support work on big-endian machines libbpf: Minor style improvements in USDT code libbpf: Fix use #ifdef instead of #if to avoid compiler warning libbpf: Potential NULL dereference in usdt_manager_attach_usdt() selftests/bpf: Uprobe tests should verify param/return values libbpf: Improve string parsing for uprobe auto-attach libbpf: Improve library identification for uprobe binary path resolution selftests/bpf: Test for writes to map key from BPF helpers selftests/bpf: Test passing rdonly mem to global func bpf: Reject writes for PTR_TO_MAP_KEY in check_helper_mem_access bpf: Check PTR_TO_MEM | MEM_RDONLY in check_helper_mem_access ... ==================== Link: https://lore.kernel.org/r/20220408231741.19116-1-daniel@iogearbox.net Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-04-08Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds11-33/+41
Pull arm64 fixes from Will Deacon: "The two main things to note are: (1) The bulk of the diffstat is us reverting a horrible bodge we had in place to ease the merging of maple tree during the merge window (which turned out not to be needed, but anyway) (2) The TLB invalidation fix is done in core code, as suggested by (and Acked-by) Peter. Summary: - Revert temporary bodge in MTE coredumping to ease maple tree integration - Fix stack frame size warning reported with 64k pages - Fix stop_machine() race with instruction text patching - Ensure alternatives patching routines are not instrumented - Enable Spectre-BHB mitigation for Cortex-A78AE - Fix hugetlb TLB invalidation when contiguous hint is used - Minor perf driver fixes - Fix some typos" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: perf/imx_ddr: Fix undefined behavior due to shift overflowing the constant arm64: Add part number for Arm Cortex-A78AE arm64: patch_text: Fixup last cpu should be master tlb: hugetlb: Add more sizes to tlb_remove_huge_tlb_entry arm64: alternatives: mark patch_alternative() as `noinstr` perf: MARVELL_CN10K_DDR_PMU should depend on ARCH_THUNDER perf: qcom_l2_pmu: fix an incorrect NULL check on list iterator arm64: Fix comments in macro __init_el2_gicv3 arm64: fix typos in comments arch/arm64: Fix topology initialization for core scheduling arm64: mte: Fix the stack frame size warning in mte_dump_tag_range() Revert "arm64: Change elfcore for_each_mte_vma() to use VMA iterator"
2022-04-08x86/PCI: Clip only host bridge windows for E820 regionsBjorn Helgaas3-7/+17
ACPI firmware advertises PCI host bridge resources via PNP0A03 _CRS methods. Some BIOSes include non-window address space in _CRS, and if we allocate that non-window space for PCI devices, they don't work. 4dc2287c1805 ("x86: avoid E820 regions when allocating address space") works around this issue by clipping out any regions mentioned in the E820 table in the allocate_resource() path, but the implementation has a couple issues: - The clipping is done for *all* allocations, not just those for PCI address space, and - The clipping is done at each allocation instead of being done once when setting up the host bridge windows. Rework the implementation so we only clip PCI host bridge windows, and we do it once when setting them up. Example output changes: BIOS-e820: [mem 0x00000000b0000000-0x00000000c00fffff] reserved + acpi PNP0A08:00: clipped [mem 0xc0000000-0xfebfffff window] to [mem 0xc0100000-0xfebfffff window] for e820 entry [mem 0xb0000000-0xc00fffff] - pci_bus 0000:00: root bus resource [mem 0xc0000000-0xfebfffff window] + pci_bus 0000:00: root bus resource [mem 0xc0100000-0xfebfffff window] Link: https://lore.kernel.org/r/20220304035110.988712-3-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-08x86: Log resource clipping for E820 regionsBjorn Helgaas1-0/+7
When remove_e820_regions() clips a resource because an E820 region overlaps it, log a note in dmesg to add in debugging. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-04-08Merge tag 'kvmarm-fixes-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEADPaolo Bonzini7-55/+101
KVM/arm64 fixes for 5.18, take #1 - Some PSCI fixes after introducing PSCIv1.1 and SYSTEM_RESET2 - Fix the MMU write-lock not being taken on THP split - Fix mixed-width VM handling - Fix potential UAF when debugfs registration fails - Various selftest updates for all of the above
2022-04-08arm64: dts: synaptics: remove unused DTSI for AS370Krzysztof Kozlowski1-173/+0
The as370.dtsi for Synaptics AS370 SoC does not have a user (DTS board file), is uncompilable and untestable. It was added back in 2018. No user appeared since that time, so assume it won't be added. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-08ARM: ixp4xx: enable multiplatform supportArnd Bergmann5-81/+16
After all the work that Linus Walleij did on this platform, it can be part of a generic kernel build as well. Note that there are known bugs in little-endian mode on ixp4xx, and no other ARMv5 platform at this point supports big-endian mode, or is likely to in the future, so there is limited practical value in this, but it helps with build testing and ixp4xx little-endian support may get fixed in the future. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-08ARM: rework endianess selectionArnd Bergmann34-33/+54
Choosing big-endian vs little-endian kernels in Kconfig has not worked correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long time ago. The problems is that CONFIG_BIG_ENDIAN depends on ARCH_SUPPORTS_BIG_ENDIAN, which can set by any one platform in the config, but would actually have to be supported by all of them. This was mostly ok for ARMv6/ARMv7 builds, since these are BE8 and tend to just work aside from problems in nonportable device drivers. For ARMv4/v5 machines, CONFIG_BIG_ENDIAN and CONFIG_ARCH_MULTIPLATFORM were never set together, so this was disabled on all those machines except for IXP4xx. As IXP4xx can now become part of ARCH_MULTIPLATFORM, it seems better to formalize this logic: all ARMv4/v5 platforms get an explicit dependency on being either big-endian (ixp4xx) or little-endian (the rest). We may want to fix ixp4xx in the future to support both, but it does not work in LE mode at the moment. For the ARMv6/v7 platforms, there are two ways this could be handled a) allow both modes only for platforms selecting 'ARCH_SUPPORTS_BIG_ENDIAN' today, but only LE mode for the others, given that these were added intentionally at some point. b) allow both modes everwhere, given that it was already possible to build that way by e.g. selecting ARCH_VIRT, and that the list is not an accurate reflection of which platforms may or may not work. Out of these, I picked b) because it seemed slighly more logical to me. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-08ARM: iop32x: enable multiplatform supportArnd Bergmann11-59/+19
After iop32x was converted to the generic multi-irq entry code, nothing really stops us from building it into a generic kernel. The two last headers can simply be removed, the mach/irqs.h gets replaced with the sparse-irq intiialization from the board specific .nr_irqs value, and the decompressor debug output can use the debug_ll hack that all other platforms use. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-08ARM: s3c: enable s3c24xx multiplatform supportArnd Bergmann5-19/+29
With the custom ISA I/O and the missing sparse-irq support out of the way, s3c24xx can now be built into the same kernel as all other ARM9 based platforms. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-08arm64: dts: imx8mp: add GPU nodesLucas Stach1-0/+31
Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP. etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: dts: imx8mp: add GPC node with GPU power domainsLucas Stach1-0/+41
Add the power domains for the GPUs, which do not require any interaction with a blk-ctrl, but are simply two PU domains nested inside a MIX domain. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: defconfig: Enable Qualcomm PCIe Gen2 PHYBjorn Andersson1-0/+1
The Qualcomm QCS404 platform uses the PCIe Gen2 PHY, enable the driver for this to ensure that PCIe is functional. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20220217040205.1898644-1-bjorn.andersson@linaro.org
2022-04-08arm64: dts: imx8mn-evk: add QSPI flashMichael Walle1-0/+27
There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. Add a device tree node for it. Tested on a 8MNANOD3L-EVK. Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08net: atm: remove the ambassador driverJakub Kicinski2-2/+0
The driver for ATM Ambassador devices spews build warnings on microblaze. The virt_to_bus() calls discard the volatile keyword. The right thing to do would be to migrate this driver to a modern DMA API but it seems unlikely anyone is actually using it. There had been no fixes or functional changes here since the git era begun. In fact it sounds like the FW loading was broken from 2008 'til 2012 - see commit fcdc90b025e6 ("atm: forever loop loading ambassador firmware"). Let's remove this driver, there isn't much changing in the APIs, if users come forward we can apologize and revert. Link: https://lore.kernel.org/all/20220321144013.440d7fc0@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com/ Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-08arm64: Add part number for Arm Cortex-A78AEChanho Park2-0/+3
Add the MIDR part number info for the Arm Cortex-A78AE[1] and add it to spectre-BHB affected list[2]. [1]: https://developer.arm.com/Processors/Cortex-A78AE [2]: https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Cc: James Morse <james.morse@arm.com> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220407091128.8700-1-chanho61.park@samsung.com Signed-off-by: Will Deacon <will@kernel.org>
2022-04-08arm64: patch_text: Fixup last cpu should be masterGuo Ren1-2/+2
These patch_text implementations are using stop_machine_cpuslocked infrastructure with atomic cpu_count. The original idea: When the master CPU patch_text, the others should wait for it. But current implementation is using the first CPU as master, which couldn't guarantee the remaining CPUs are waiting. This patch changes the last CPU as the master to solve the potential risk. Fixes: ae16480785de ("arm64: introduce interfaces to hotpatch kernel and module code") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20220407073323.743224-2-guoren@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-04-08arm64: dts: imx8mq-librem5-r4: add the correct panelGuido Günther1-0/+4
The r4 ("Evergreen") hardware revision of the Librem 5 phone includes a slightly different panel than the revisions before it. Since its' description is available, describe it properly for the board. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: dts: imx8mq-librem5: add a RO firmware partitionAngus Ainslie1-7/+2
This partition will hold a squashfs firmware jail. Only one read-only partition is needed. Signed-off-by: Angus Ainslie <angus@akkea.ca> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: dts: imx8mq-librem5: higher boost regulation currentGuido Günther1-1/+1
1,5A is what's used by the type-c controller on the Librem 5 board so increase ti,boost-max-current to 1,5A too. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: dts: imx8mq-librem5: remove description of CHG_STATUS_BMartin Kepplinger1-2/+0
That pin is not connected on the board so no need to describe it. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08arm64: dts: imx8mq-librem5: make the volume buttons a wakeup sourceMartin Kepplinger1-0/+2
They turn on the display currently so to be consistent, let's make them wake the system from suspend as well. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-08x86/sev-es: Replace open-coded hlt-loop with sev_es_terminate()Peter Gonda1-2/+1
Replace the halt loop in handle_vc_boot_ghcb() with an sev_es_terminate(). The HLT gives the system no indication the guest is unhappy. The termination request will signal there was an error during VC handling during boot. [ bp: Update it to pass the reason set too. ] Signed-off-by: Peter Gonda <pgonda@google.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Joerg Roedel <jroedel@suse.de> Link: https://lore.kernel.org/r/20220317211913.1397427-1-pgonda@google.com
2022-04-08crypto: x86 - eliminate anonymous module_init & module_exitRandy Dunlap5-20/+20
Eliminate anonymous module_init() and module_exit(), which can lead to confusion or ambiguity when reading System.map, crashes/oops/bugs, or an initcall_debug log. Give each of these init and exit functions unique driver-specific names to eliminate the anonymous names. Example 1: (System.map) ffffffff832fc78c t init ffffffff832fc79e t init ffffffff832fc8f8 t init Example 2: (initcall_debug log) calling init+0x0/0x12 @ 1 initcall init+0x0/0x12 returned 0 after 15 usecs calling init+0x0/0x60 @ 1 initcall init+0x0/0x60 returned 0 after 2 usecs calling init+0x0/0x9a @ 1 initcall init+0x0/0x9a returned 0 after 74 usecs Fixes: 64b94ceae8c1 ("crypto: blowfish - add x86_64 assembly implementation") Fixes: 676a38046f4f ("crypto: camellia-x86_64 - module init/exit functions should be static") Fixes: 0b95ec56ae19 ("crypto: camellia - add assembler implementation for x86_64") Fixes: 56d76c96a9f3 ("crypto: serpent - add AVX2/x86_64 assembler implementation of serpent cipher") Fixes: b9f535ffe38f ("[CRYPTO] twofish: i586 assembly version") Fixes: ff0a70fe0536 ("crypto: twofish-x86_64-3way - module init/exit functions should be static") Fixes: 8280daad436e ("crypto: twofish - add 3-way parallel x86_64 assembler implemention") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Cc: Joachim Fritschi <jfritschi@freenet.de> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Cc: x86@kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-04-08crypto: arm64/sm4 - add ARMv8 Crypto Extensions implementationTianjia Zhang4-0/+1041
This adds ARMv8 implementations of SM4 in ECB, CBC, CFB and CTR modes using Crypto Extensions, also includes key expansion operations because the Crypto Extensions instruction is much faster than software implementations. The Crypto Extensions for SM4 can only run on ARMv8 implementations that have support for these optional extensions. Benchmark on T-Head Yitian-710 2.75 GHz, the data comes from the 218 mode of tcrypt. The abscissas are blocks of different lengths. The data is tabulated and the unit is Mb/s: sm4-generic | 16 64 128 256 1024 1420 4096 ECB enc | 80.05 91.42 93.66 94.77 95.69 95.77 95.86 ECB dec | 79.98 91.41 93.64 94.76 95.66 95.77 95.85 CBC enc | 78.55 86.50 88.02 88.77 89.36 89.42 89.48 CBC dec | 76.82 89.06 91.52 92.77 93.75 93.83 93.96 CFB enc | 77.64 86.13 87.62 88.42 89.08 88.83 89.18 CFB dec | 77.57 88.34 90.36 91.45 92.34 92.00 92.44 CTR enc | 77.80 88.28 90.23 91.22 92.11 91.81 92.25 CTR dec | 77.83 88.22 90.22 91.22 92.04 91.82 92.28 sm4-neon ECB enc | 28.31 112.77 203.03 209.89 215.49 202.11 210.59 ECB dec | 28.36 113.45 203.23 210.00 215.52 202.13 210.65 CBC enc | 79.32 87.02 88.51 89.28 89.85 89.89 89.97 CBC dec | 28.29 112.20 203.30 209.82 214.99 201.51 209.95 CFB enc | 79.59 87.16 88.54 89.30 89.83 89.62 89.92 CFB dec | 28.12 111.05 202.47 209.02 214.21 210.90 209.12 CTR enc | 28.04 108.81 200.62 206.65 211.78 208.78 206.74 CTR dec | 28.02 108.82 200.45 206.62 211.78 208.74 206.70 sm4-ce-cipher ECB enc | 336.79 587.13 682.70 747.37 803.75 811.52 818.06 ECB dec | 339.18 584.52 679.72 743.68 798.82 803.83 811.54 CBC enc | 316.63 521.47 597.00 647.14 690.82 695.21 700.55 CBC dec | 291.80 503.79 585.66 640.82 689.86 695.16 701.72 CFB enc | 294.79 482.31 552.13 594.71 631.60 628.91 638.92 CFB dec | 293.09 466.44 526.56 563.17 594.41 592.26 601.97 CTR enc | 309.61 506.13 576.86 620.47 656.38 654.51 665.10 CTR dec | 306.69 505.57 576.84 620.18 657.09 654.52 665.32 sm4-ce ECB enc | 366.96 1329.81 2024.29 2755.50 3790.07 3861.91 4051.40 ECB dec | 367.30 1323.93 2018.72 2747.43 3787.39 3862.55 4052.62 CBC enc | 358.09 682.68 807.24 885.35 958.29 963.60 973.73 CBC dec | 366.51 1303.63 1978.64 2667.93 3624.53 3683.41 3856.08 CFB enc | 351.51 681.26 807.81 893.10 968.54 969.17 985.83 CFB dec | 354.98 1266.61 1929.63 2634.81 3614.23 3611.59 3841.68 CTR enc | 324.23 1121.25 1689.44 2256.70 2981.90 3007.79 3060.74 CTR dec | 324.18 1120.44 1694.31 2258.32 2982.01 3010.09 3060.99 Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-04-08crypto: arm64/sm4 - add ARMv8 NEON implementationTianjia Zhang4-0/+938
This adds ARMv8 NEON implementations of SM4 in ECB, CBC, CFB and CTR modes. This implementation uses the plain NEON instruction set, All S-BOX substitutions uses the tbl/tbx instructions of ARMv8, combined with the out-of-order execution in CPU, this optimization supports encryption of up to 8 blocks at the same time. The performance of encrypting one block is not as good as software implementation, so the encryption operations of CBC and CFB still use pure software algorithms. Benchmark on T-Head Yitian-710 2.75 GHz, the data comes from the 218 mode of tcrypt. The abscissas are blocks of different lengths. The data is tabulated and the unit is Mb/s: sm4-generic | 16 64 128 256 1024 1420 4096 ECB enc | 80.05 91.42 93.66 94.77 95.69 95.77 95.86 ECB dec | 79.98 91.41 93.64 94.76 95.66 95.77 95.85 CBC enc | 78.55 86.50 88.02 88.77 89.36 89.42 89.48 CBC dec | 76.82 89.06 91.52 92.77 93.75 93.83 93.96 CFB enc | 77.64 86.13 87.62 88.42 89.08 88.83 89.18 CFB dec | 77.57 88.34 90.36 91.45 92.34 92.00 92.44 CTR enc | 77.80 88.28 90.23 91.22 92.11 91.81 92.25 CTR dec | 77.83 88.22 90.22 91.22 92.04 91.82 92.28 sm4-neon ECB enc | 28.31 112.77 203.03 209.89 215.49 202.11 210.59 ECB dec | 28.36 113.45 203.23 210.00 215.52 202.13 210.65 CBC enc | 79.32 87.02 88.51 89.28 89.85 89.89 89.97 CBC dec | 28.29 112.20 203.30 209.82 214.99 201.51 209.95 CFB enc | 79.59 87.16 88.54 89.30 89.83 89.62 89.92 CFB dec | 28.12 111.05 202.47 209.02 214.21 210.90 209.12 CTR enc | 28.04 108.81 200.62 206.65 211.78 208.78 206.74 CTR dec | 28.02 108.82 200.45 206.62 211.78 208.74 206.70 Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-04-08crypto: arm64/sm4-ce - rename to sm4-ce-cipherTianjia Zhang3-3/+3
The subsequent patches of the series will have an implementation of SM4-ECB/CBC/CFB/CTR accelerated by the CE instruction set, which conflicts with the current module name. In order to keep the naming rules of the AES algorithm consistent, the sm4-ce algorithm is renamed to sm4-ce-cipher. In addition, the speed of sm4-ce-cipher is better than that of SM4 NEON. By the way, the priority of the algorithm is adjusted to 300, which is also to leave room for the priority of SM4 NEON. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-04-08crypto: sm3,sm4 - move into crypto directoryJason A. Donenfeld1-2/+2
The lib/crypto libraries live in lib because they are used by various drivers of the kernel. In contrast, the various helper functions in crypto are there because they're used exclusively by the crypto API. The SM3 and SM4 helper functions were erroniously moved into lib/crypto/ instead of crypto/, even though there are no in-kernel users outside of the crypto API of those functions. This commit moves them into crypto/. Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Cc: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-04-08ARM: dts: meson: align SPI NOR node name with dtschemaKrzysztof Kozlowski1-1/+1
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220407142159.293836-1-krzysztof.kozlowski@linaro.org
2022-04-08arm64: dts: meson: align SPI NOR node name with dtschemaKrzysztof Kozlowski6-6/+6
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220407142159.293836-2-krzysztof.kozlowski@linaro.org
2022-04-08arm64: dts: remove cpu compatible "arm,armv8" for s4Xianwei Zhao1-4/+4
Amlogic s4 device is already applied, but cpu compatible 'arm,armv8' is only valid for software models, so we remove it. Fixes: ac4dfd0d1d35 ("arm64: dts: add support for S4 based Amlogic AQ222") Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220408070901.26446-1-xianwei.zhao@amlogic.com
2022-04-08csky: Fix versioncheck warningsDeyan Wang3-3/+0
$make versioncheck arch/csky/include/asm/io.h: 8 linux/version.h not needed. arch/csky/kernel/process.c: 5 linux/version.h not needed. arch/csky/mm/dma-mapping.c: 12 linux/version.h not needed. comments from Randy: The patch makes sense but these are not compile warnings. They come from scripts/checkversion.pl, which can be called by 'make versioncheck', so I suppose that something in your build system is running 'make versioncheck'. Signed-off-by: Deyan Wang <wonder_rock@126.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org>
2022-04-07Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-2/+19
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-04-07arm64: defconfig: Enable SM8250 video clock controllerBryan O'Donoghue1-0/+1
Enable the building of the sm8250 video clock controller by default. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220131202721.2122605-2-dmitry.baryshkov@linaro.org
2022-04-07arm64: defconfig: Enable PM8916 watchdog driverAníbal Limón1-0/+1
Enable watchdog driver for pm8916 block. It is used on msm8916/apq8016 platforms (e.g. Dragonboard 410c). Signed-off-by: Aníbal Limón <anibal.limon@linaro.org> [DB: changed to =m, expanded commit message] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220131202721.2122605-1-dmitry.baryshkov@linaro.org
2022-04-07arm64: defconfig: enable ath11k driverDmitry Baryshkov1-0/+4
Enable Atheros Ath11k driver to be built on arm64 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220131165056.2117434-2-dmitry.baryshkov@linaro.org
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