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2022-02-16ARM: mstar: Add OPP table for infinity3Daniel Palmer1-0/+58
The infinity3 has a slightly higher max frequency compared to the infinity so extend the OPP table. Co-authored-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Add OPP table for infinityDaniel Palmer1-0/+34
Add an OPP table for the inifinity chips so that cpu frequency scaling can happen. Co-authored-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Link cpupll to second coreDaniel Palmer1-0/+2
The second core also sources it's clock from the CPU PLL. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Link cpupll to cpuDaniel Palmer1-0/+2
The CPU clock is sourced from the CPU PLL. Link cpupll to the cpu so that frequency scaling can happen. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Add cpupll to base dtsiDaniel Palmer1-0/+7
All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16arm64: dts: ti: k3-am64: Add ESM0 to device memory mapHari Nagalla1-0/+1
AM64x SoCs have two ESM modules, with one in MAIN voltage domain and the other in MCU voltage domain. The error output from Main ESM module can be routed to the MCU ESM module. The error output of MCU ESM can be configured to reset the device. The MCU ESM configuration address space is already opened and this patch opens the MAIN ESM configuration address space. For ESM details please refer technical reference manual at https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Link: https://lore.kernel.org/r/20220210172246.27871-1-hnagalla@ti.com
2022-02-16arm64: dts: ti: k3-am65*: Remove #address-cells/#size-cells from flash nodesMatthias Schiffer2-8/+2
Specifying partitions directly in the flash node is deprecated, a fixed-partitions node should be used instead. Therefore, it doesn't make sense to have these properties in the flash nodes. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20220203140240.973690-2-matthias.schiffer@ew.tq-group.com
2022-02-16arm64: defconfig: tegra: Enable GPCDMAAkhil R1-0/+1
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc dma controller driver Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-16sched/isolation: Use single feature type while referring to housekeeping cpumaskFrederic Weisbecker2-4/+4
Refer to housekeeping APIs using single feature types instead of flags. This prevents from passing multiple isolation features at once to housekeeping interfaces, which soon won't be possible anymore as each isolation features will have their own cpumask. Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Juri Lelli <juri.lelli@redhat.com> Reviewed-by: Phil Auld <pauld@redhat.com> Link: https://lore.kernel.org/r/20220207155910.527133-5-frederic@kernel.org
2022-02-16arm64: proton-pack: Report Spectre-BHB vulnerabilities as part of Spectre-v2James Morse2-2/+36
Speculation attacks against some high-performance processors can make use of branch history to influence future speculation as part of a spectre-v2 attack. This is not mitigated by CSV2, meaning CPUs that previously reported 'Not affected' are now moderately mitigated by CSV2. Update the value in /sys/devices/system/cpu/vulnerabilities/spectre_v2 to also show the state of the BHB mitigation. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-16arm64: Add percpu vectors for EL1James Morse4-9/+53
The Spectre-BHB workaround adds a firmware call to the vectors. This is needed on some CPUs, but not others. To avoid the unaffected CPU in a big/little pair from making the firmware call, create per cpu vectors. The per-cpu vectors only apply when returning from EL0. Systems using KPTI can use the canonical 'full-fat' vectors directly at EL1, the trampoline exit code will switch to this_cpu_vector on exit to EL0. Systems not using KPTI should always use this_cpu_vector. this_cpu_vector will point at a vector in tramp_vecs or __bp_harden_el1_vectors, depending on whether KPTI is in use. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-16arm64: entry: Add macro for reading symbol addresses from the trampolineJames Morse1-21/+16
The trampoline code needs to use the address of symbols in the wider kernel, e.g. vectors. PC-relative addressing wouldn't work as the trampoline code doesn't run at the address the linker expected. tramp_ventry uses a literal pool, unless CONFIG_RANDOMIZE_BASE is set, in which case it uses the data page as a literal pool because the data page can be unmapped when running in user-space, which is required for CPUs vulnerable to meltdown. Pull this logic out as a macro, instead of adding a third copy of it. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-16arm64: entry: Add vectors that have the bhb mitigation sequencesJames Morse4-9/+118
Some CPUs affected by Spectre-BHB need a sequence of branches, or a firmware call to be run before any indirect branch. This needs to go in the vectors. No CPU needs both. While this can be patched in, it would run on all CPUs as there is a single set of vectors. If only one part of a big/little combination is affected, the unaffected CPUs have to run the mitigation too. Create extra vectors that include the sequence. Subsequent patches will allow affected CPUs to select this set of vectors. Later patches will modify the loop count to match what the CPU requires. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-16asm-generic: Refactor dereference_[kernel]_function_descriptor()Christophe Leroy4-72/+0
dereference_function_descriptor() and dereference_kernel_function_descriptor() are identical on the three architectures implementing them. Make them common and put them out-of-line in kernel/extable.c which is one of the users and has similar type of functions. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Helge Deller <deller@gmx.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/449db09b2eba57f4ab05f80102a67d8675bc8bcd.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16asm-generic: Define 'func_desc_t' to commonly describe function descriptorsChristophe Leroy4-8/+12
We have three architectures using function descriptors, each with its own type and name. Add a common typedef that can be used in generic code. Also add a stub typedef for architecture without function descriptors, to avoid a forest of #ifdefs. It replaces the similar 'func_desc_t' previously defined in arch/powerpc/kernel/module_64.c Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Helge Deller <deller@gmx.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/f1f91b142b3c1082bdc1586ce71c9bac1e75213c.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16asm-generic: Define CONFIG_HAVE_FUNCTION_DESCRIPTORSChristophe Leroy8-6/+12
Replace HAVE_DEREFERENCE_FUNCTION_DESCRIPTOR by a config option named CONFIG_HAVE_FUNCTION_DESCRIPTORS and use it instead of 'dereference_function_descriptor' macro to know whether an arch has function descriptors. To limit churn in one of the following patches, use an #ifdef/#else construct with empty first part instead of an #ifndef in asm-generic/sections.h On powerpc, make sure the config option matches the ABI used by the compiler with a BUILD_BUG_ON() and add missing _CALL_ELF=2 when calling 'sparse' so that sparse sees the same piece of code as GCC. And include a helper to check whether an arch has function descriptors or not : have_function_descriptors() Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Helge Deller <deller@gmx.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/4a0f11fb0ea74a3197bc44dd7ba25e53a24fd03d.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16ia64: Rename 'ip' to 'addr' in 'struct fdesc'Christophe Leroy3-5/+5
There are three architectures with function descriptors, try to have common names for the address they contain in order to refactor some functions into generic functions later. powerpc has 'entry' ia64 has 'ip' parisc has 'addr' Vote for 'addr' and update 'struct fdesc' accordingly. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/65b73ac614e4c002c5819d40b42f6f426d2ee52b.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16powerpc: Prepare func_desc_t for refactorisationChristophe Leroy1-18/+18
In preparation of making func_desc_t generic, change the ELFv2 version to a struct containing 'addr' element. This allows using single helpers common to ELFv1 and ELFv2 and reduces the amount of #ifdef's Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/5c36105e08b27b98450535bff48d71b690c19739.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16powerpc: Remove 'struct ppc64_opd_entry'Christophe Leroy1-8/+0
'struct ppc64_opd_entry' doesn't belong to uapi/asm/elf.h It was initially in module_64.c and commit 2d291e902791 ("Fix compile failure with non modular builds") moved it into asm/elf.h But it was by mistake added outside of __KERNEL__ section, therefore commit c3617f72036c ("UAPI: (Scripted) Disintegrate arch/powerpc/include/asm") moved it to uapi/asm/elf.h Now that it is not used anymore by the kernel, remove it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/c309ccee65ec2e3802df7a7fe761d0a298584809.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16powerpc: Use 'struct func_desc' instead of 'struct ppc64_opd_entry'Christophe Leroy2-7/+7
'struct ppc64_opd_entry' is somehow redundant with 'struct func_desc', the later is more correct/complete as it includes the third field which is unused. So use 'struct func_desc' instead of 'struct ppc64_opd_entry' Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Daniel Axtens <dja@axtens.net> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/34e76bac6cbe95a63ecd37df69fb7feb93b0ea7c.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16powerpc: Move and rename func_descr_tChristophe Leroy4-11/+11
There are three architectures with function descriptors, try to have common names for the address they contain in order to refactor some functions into generic functions later. powerpc has 'entry' ia64 has 'ip' parisc has 'addr' Vote for 'addr' and update 'func_descr_t' accordingly. Move it in asm/elf.h to have it at the same place on all three architectures, remove the typedef which hides its real type, and change it to a smoother name 'struct func_desc'. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/529b2ba1d001e8f628ef0d30e8044c9b3d0a4921.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16powerpc: Fix 'sparse' checking on PPC64leChristophe Leroy1-1/+1
'sparse' is architecture agnostic and knows nothing about ELF ABI version. Just like it gets arch and powerpc type and endian from Makefile, it also need to get _CALL_ELF from there, otherwise it won't set PPC64_ELF_ABI_v2 macro for PPC64le and won't check the correct code. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/ac1312f2451aa558bb2a8806b4d0aa2020f0c176.1644928018.git.christophe.leroy@csgroup.eu
2022-02-16powerpc/papr_scm: Implement initial support for injecting smart errorsVaibhav Jain2-3/+105
Presently PAPR doesn't support injecting smart errors on an NVDIMM. This makes testing the NVDIMM health reporting functionality difficult as simulating NVDIMM health related events need a hacked up qemu version. To solve this problem this patch proposes simulating certain set of NVDIMM health related events in papr_scm. Specifically 'fatal' health state and 'dirty' shutdown state. These error can be injected via the user-space 'ndctl-inject-smart(1)' command. With the proposed patch and corresponding ndctl patches following command flow is expected: $ sudo ndctl list -DH -d nmem0 ... "health_state":"ok", "shutdown_state":"clean", ... # inject unsafe shutdown and fatal health error $ sudo ndctl inject-smart nmem0 -Uf ... "health_state":"fatal", "shutdown_state":"dirty", ... # uninject all errors $ sudo ndctl inject-smart nmem0 -N ... "health_state":"ok", "shutdown_state":"clean", ... The patch adds a new member 'health_bitmap_inject_mask' inside struct papr_scm_priv which is then bitwise ANDed to the health bitmap fetched from the hypervisor. The value for 'health_bitmap_inject_mask' is accessible from sysfs at nmemX/papr/health_bitmap_inject. A new PDSM named 'SMART_INJECT' is proposed that accepts newly introduced 'struct nd_papr_pdsm_smart_inject' as payload thats exchanged between libndctl and papr_scm to indicate the requested smart-error states. When the processing the PDSM 'SMART_INJECT', papr_pdsm_smart_inject() constructs a pair or 'inject_mask' and 'clear_mask' bitmaps from the payload and bit-blt it to the 'health_bitmap_inject_mask'. This ensures the after being fetched from the hypervisor, the health_bitmap reflects requested smart-error states. Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220124202204.1488346-1-vaibhav@linux.ibm.com
2022-02-16powerpc/ftrace: Style cleanup in ftrace_mprofile.SChristophe Leroy1-4/+8
Add some line breaks to better match the file's style, add some space after comma and fix a couple of misplaced blanks. Suggested-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/973506292d0c7b05c06530c8e11803ce38e5eda2.1644949750.git.christophe.leroy@csgroup.eu
2022-02-16powerpc/ftrace: Have arch_ftrace_get_regs() return NULL unless FL_SAVE_REGS is setChristophe Leroy2-1/+6
When FL_SAVE_REGS is not set we get here via ftrace_caller() which doesn't save all registers. ftrace_caller() explicitely clears regs.msr, so we can rely on it to know where we come from. We don't expect MSR register to be 0 at all when involving ftrace. Fixes: 40b035efe288 ("powerpc/ftrace: Implement CONFIG_DYNAMIC_FTRACE_WITH_ARGS") Reported-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/2f9a7e898c93cc7438ef5ccd47cb9c3a9c5b53ef.1644949750.git.christophe.leroy@csgroup.eu
2022-02-16powerpc/ftrace: Add recursion protection in prepare_ftrace_return()Christophe Leroy1-0/+7
The function_graph_enter() does not provide any recursion protection. Add a protection in prepare_ftrace_return() in case function_graph_enter() calls something that gets function graph traced. Fixes: 830213786c49 ("powerpc/ftrace: directly call of function graph tracer by ftrace caller") Reported-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/74edf2ff0a60e66b0d9225a137100a86a0557032.1644949750.git.christophe.leroy@csgroup.eu
2022-02-16powerpc/ftrace: Also save r1 in ftrace_caller()Christophe Leroy1-0/+4
Also save r1 in ftrace_caller() r1 is needed during unwinding when the function_graph tracer is active. Fixes: 830213786c49 ("powerpc/ftrace: directly call of function graph tracer by ftrace caller") Reported-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/ff535e86d3a69376a6d89168511d4e403835f18b.1644949750.git.christophe.leroy@csgroup.eu
2022-02-16ARM: dts: aspeed: bletchley: Cleanup redundant nodesPotin Lai1-8/+1
Cleanup following nodes: 1. Remove redundant i2c1 node. 2. Disable in-chip rtc, use battery-backed external rtc (pcf85263) instead. Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-11-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Enable mdio3 busPotin Lai1-0/+5
Enable mdio3 bus based on EVT HW. So far lack of c45 support in mdio-aspeed, at least can access mdio bus by read/write register. TODO: Add Marvell PHY 88X3310 and mdio-aspeed driver c45 support Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-10-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Add INA230 sensor on each sledPotin Lai1-6/+30
Add INA230 node on each sled based on EVT HW. Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-9-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Add shunt-resistor for ADM1278Potin Lai1-0/+1
Fix with correct shunt-resistor value base on EVT HW. Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-8-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Add interrupt support for sled io expanderPotin Lai1-0/+19
Enable interrupt support for all sledx_ioexp, so userspace can monitor gpio from io expander by interrupt. Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-7-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Switch to spi-gpio for spi2Potin Lai1-14/+21
Switch spi2 to spi-gpio driver to avoid unstable signal issue with EVT HW. Remove spi2 node and create a new spi2_gpio node. Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-6-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Update fmc configurationsPotin Lai1-0/+6
Add flash1 in fmc to support dual flash module. Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-5-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Update gpio-line-namesPotin Lai1-12/+14
Update gpio-line-names based on EVT HW schematic - gpio0: - BSM_FRU_WP (G0, out) - PWRGD_P1V05_VDDCORE (G4, in) - PWRGD_P1V5_VDD (G5, in) - BSM_FLASH_WP_STATUS (I5, in) - BMC_TPM_PRES (I6, in) - BMC_RTC_INT (L5, in) - BMC_HEARTBEAT (P7, out) - PWRGD_CNS_PSU (V0, in) - PSU_PRSNT (V3, in) - BMC_SELF_HW_RST (Y0, out) - BSM_PRSNT (Y1, in) - sled1_led pca9522: - SLED1_MD_REF_PWM (3, out) - sled2_led pca9522: - SLED2_MD_REF_PWM (3, out) - sled3_led pca9522: - SLED3_MD_REF_PWM (3, out) - sled4_led pca9522: - SLED4_MD_REF_PWM (3, out) - sled5_led pca9522: - SLED5_MD_REF_PWM (3, out) - sled6_led pca9522: - SLED6_MD_REF_PWM (3, out) Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-4-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Separate leds into multiple groupsPotin Lai1-25/+52
Separate gpio-leds by each io expander chip. To avoid entire gpio-leds bind failed due to single chip not available Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-3-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-16ARM: dts: aspeed: bletchley: Switch sled numbering to 1-basedPotin Lai1-64/+64
Switch sled to 1-based to meet OpenBMC multi-host numbering rule Signed-off-by: Potin Lai <potin.lai@quantatw.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220215163151.32252-2-potin.lai@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-15arm64: mte: Dump the MTE tags in the core fileCatalin Marinas3-0/+125
For each vma mapped with PROT_MTE (the VM_MTE flag set), generate a PT_ARM_MEMTAG_MTE segment in the core file and dump the corresponding tags. The in-file size for such segments is 128 bytes per page. For pages in a VM_MTE vma which are not present in the user page tables or don't have the PG_mte_tagged flag set (e.g. execute-only), just write zeros in the core file. An example of program headers for two vmas, one 2-page, the other 4-page long: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align ... LOAD 0x030000 0x0000ffff80034000 0x0000000000000000 0x000000 0x002000 RW 0x1000 LOAD 0x030000 0x0000ffff80036000 0x0000000000000000 0x004000 0x004000 RW 0x1000 ... LOPROC+0x1 0x05b000 0x0000ffff80034000 0x0000000000000000 0x000100 0x002000 0 LOPROC+0x1 0x05b100 0x0000ffff80036000 0x0000000000000000 0x000200 0x004000 0 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Luis Machado <luis.machado@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220131165456.2160675-5-catalin.marinas@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-15arm64: mte: Define the number of bytes for storing the tags in a pageCatalin Marinas3-3/+4
Rather than explicitly calculating the number of bytes for a compact tag storage format corresponding to a page, just add a MTE_PAGE_TAG_STORAGE macro. With the current MTE implementation of 4 bits per tag, we store 2 tags in a byte. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Luis Machado <luis.machado@linaro.org> Link: https://lore.kernel.org/r/20220131165456.2160675-4-catalin.marinas@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-15elfcore: Replace CONFIG_{IA64, UML} checks with a new optionCatalin Marinas2-0/+2
As arm64 is about to introduce MTE-specific phdrs in the core dump, add a common CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS option currently selectable by UML_X86 and IA64. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Eric Biederman <ebiederm@xmission.com> Link: https://lore.kernel.org/r/20220131165456.2160675-2-catalin.marinas@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-15arm64: dts: broadcom: bcm4908: add I2C blockRafał Miłecki1-0/+9
BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-02-15Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds12-142/+232
Pull kvm fixes from Paolo Bonzini: "ARM: - Read HW interrupt pending state from the HW x86: - Don't truncate the performance event mask on AMD - Fix Xen runstate updates to be atomic when preempting vCPU - Fix for AMD AVIC interrupt injection race - Several other AMD fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86/pmu: Use AMD64_RAW_EVENT_MASK for PERF_TYPE_RAW KVM: x86/pmu: Don't truncate the PerfEvtSeln MSR when creating a perf event KVM: SVM: fix race between interrupt delivery and AVIC inhibition KVM: SVM: set IRR in svm_deliver_interrupt KVM: SVM: extract avic_ring_doorbell selftests: kvm: Remove absent target file KVM: arm64: vgic: Read HW interrupt pending state from the HW KVM: x86/xen: Fix runstate updates to be atomic when preempting vCPU KVM: x86: SVM: move avic definitions from AMD's spec to svm.h KVM: x86: lapic: don't touch irr_pending in kvm_apic_update_apicv when inhibiting it KVM: x86: nSVM: deal with L1 hypervisor that intercepts interrupts but lets L2 control them KVM: x86: nSVM: expose clean bit support to the guest KVM: x86: nSVM/nVMX: set nested_run_pending on VM entry which is a result of RSM KVM: x86: nSVM: mark vmcb01 as dirty when restoring SMM saved state KVM: x86: nSVM: fix potential NULL derefernce on nested migration KVM: x86: SVM: don't passthrough SMAP/SMEP/PKE bits in !NPT && !gCR0.PG case Revert "svm: Add warning message for AVIC IPI invalid target"
2022-02-15arm64: atomics: remove redundant static branchMark Rutland1-4/+2
Due to a historical oversight, we emit a redundant static branch for each atomic/atomic64 operation when CONFIG_ARM64_LSE_ATOMICS is selected. We can safely remove this, making the kernel Image reasonably smaller. When CONFIG_ARM64_LSE_ATOMICS is selected, every LSE atomic operation has two preceding static branches with the same target, e.g. b f7c <kernel_init_freeable+0xa4> b f7c <kernel_init_freeable+0xa4> mov w0, #0x1 // #1 ldadd w0, w0, [x19] This is because the __lse_ll_sc_body() wrapper uses system_uses_lse_atomics(), which checks both `arm64_const_caps_ready` and `cpu_hwcap_keys[ARM64_HAS_LSE_ATOMICS]`, each of which emits a static branch. This has been the case since commit: addfc38672c73efd ("arm64: atomics: avoid out-of-line ll/sc atomics") However, there was never a need to check `arm64_const_caps_ready`, which was itself introduced in commit: 63a1e1c95e60e798 ("arm64/cpufeature: don't use mutex in bringup path") ... so that cpus_have_const_cap() could fall back to checking the `cpu_hwcaps` bitmap prior to the static keys for individual caps becoming enabled. As system_uses_lse_atomics() doesn't check `cpu_hwcaps`, and doesn't need to as we can safely use the LL/SC atomics prior to enabling the `ARM64_HAS_LSE_ATOMICS` static key, it doesn't need to check `arm64_const_caps_ready`. This patch removes the `arm64_const_caps_ready` check from system_uses_lse_atomics(). As the arch_atomic_* routines are meant to be safely usable in noinstr code, I've also marked system_uses_lse_atomics() as __always_inline. This results in one fewer static branch per atomic operation, with the prior example becoming: b f78 <kernel_init_freeable+0xa0> mov w0, #0x1 // #1 ldadd w0, w0, [x19] Each static branch consists of the branch itself and an associated __jump_table entry. Removing these has a reasonable impact on the Image size, with a GCC 11.1.0 defconfig v5.17-rc2 Image being reduced by 128KiB: | [mark@lakrids:~/src/linux]% ls -al Image* | -rw-r--r-- 1 mark mark 34619904 Feb 3 18:24 Image.baseline | -rw-r--r-- 1 mark mark 34488832 Feb 3 18:33 Image.onebranch Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Suzuki Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20220204104439.270567-1-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-15arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigationsJames Morse1-1/+34
kpti is an optional feature, for systems not using kpti a set of vectors for the spectre-bhb mitigations is needed. Add another set of vectors, __bp_harden_el1_vectors, that will be used if a mitigation is needed and kpti is not in use. The EL1 ventries are repeated verbatim as there is no additional work needed for entry from EL1. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-15arm64: entry: Allow the trampoline text to occupy multiple pagesJames Morse5-7/+20
Adding a second set of vectors to .entry.tramp.text will make it larger than a single 4K page. Allow the trampoline text to occupy up to three pages by adding two more fixmap slots. Previous changes to tramp_valias allowed it to reach beyond a single page. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-15arm64: entry: Make the kpti trampoline's kpti sequence optionalJames Morse1-6/+12
Spectre-BHB needs to add sequences to the vectors. Having one global set of vectors is a problem for big/little systems where the sequence is costly on cpus that are not vulnerable. Making the vectors per-cpu in the style of KVM's bh_harden_hyp_vecs requires the vectors to be generated by macros. Make the kpti re-mapping of the kernel optional, so the macros can be used without kpti. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-15arm64: entry: Move trampoline macros out of ifdef'd sectionJames Morse1-6/+5
The macros for building the kpti trampoline are all behind CONFIG_UNMAP_KERNEL_AT_EL0, and in a region that outputs to the .entry.tramp.text section. Move the macros out so they can be used to generate other kinds of trampoline. Only the symbols need to be guarded by CONFIG_UNMAP_KERNEL_AT_EL0 and appear in the .entry.tramp.text section. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-15arm64: entry: Don't assume tramp_vectors is the start of the vectorsJames Morse1-13/+15
The tramp_ventry macro uses tramp_vectors as the address of the vectors when calculating which ventry in the 'full fat' vectors to branch to. While there is one set of tramp_vectors, this will be true. Adding multiple sets of vectors will break this assumption. Move the generation of the vectors to a macro, and pass the start of the vectors as an argument to tramp_ventry. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-15arm64: entry: Allow tramp_alias to access symbols after the 4K boundaryJames Morse1-5/+8
Systems using kpti enter and exit the kernel through a trampoline mapping that is always mapped, even when the kernel is not. tramp_valias is a macro to find the address of a symbol in the trampoline mapping. Adding extra sets of vectors will expand the size of the entry.tramp.text section to beyond 4K. tramp_valias will be unable to generate addresses for symbols beyond 4K as it uses the 12 bit immediate of the add instruction. As there are now two registers available when tramp_alias is called, use the extra register to avoid the 4K limit of the 12 bit immediate. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-15arm64: entry: Move the trampoline data page before the text pageJames Morse2-3/+8
The trampoline code has a data page that holds the address of the vectors, which is unmapped when running in user-space. This ensures that with CONFIG_RANDOMIZE_BASE, the randomised address of the kernel can't be discovered until after the kernel has been mapped. If the trampoline text page is extended to include multiple sets of vectors, it will be larger than a single page, making it tricky to find the data page without knowing the size of the trampoline text pages, which will vary with PAGE_SIZE. Move the data page to appear before the text page. This allows the data page to be found without knowing the size of the trampoline text pages. 'tramp_vectors' is used to refer to the beginning of the .entry.tramp.text section, do that explicitly. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
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