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2022-02-06s390/lgr: use simple assignment instead of memcpyHeiko Carstens1-2/+1
It is quite pointless to use memcpy to copy two bytes, besides that this construct will also partially remove type and size sanity checks. Therefore simply use an assignment. Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2022-02-06s390/dump: fix os_info virtual vs physical address confusionAlexander Gordeev1-2/+2
Due to historical reasons os_info handling functions misuse the notion of physical vs virtual addresses difference. Note: this does not fix a bug currently, since virtual and physical addresses are identical. Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2022-02-06s390/maccess: fix absolute lowcore virtual vs physical address confusionAlexander Gordeev1-8/+9
Due to historical reasons memcpy_absolute() and friend functions misuse the notion of physical vs virtual addresses difference. Note: this does not fix a bug currently, since virtual and physical addresses are identical. Reviewed-by: Sven Schnelle <svens@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2022-02-06s390/ftrace: verify opcode before applying patchSven Schnelle1-16/+27
commit 72b3942a173c ("scripts: ftrace - move the sort-processing in ftrace_init") had the unexpected side effect that wrong code locations were patched. To prevent this from happening again, verify the opcode before patching it. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2022-02-06s390: remove invalid email address of Heiko CarstensHeiko Carstens23-28/+3
Remove my old invalid email address which can be found in a couple of files. Instead of updating it, just remove my contact data completely from source files. We have git and other tools which allow to figure out who is responsible for what with recent contact data. Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2022-02-06s390/module: fix building test_modules_helpers.o with clangIlya Leoshkevich2-3/+3
Move test_modules_return_* prototypes into a header file in order to placate -Wmissing-prototypes. Fixes: 90c5318795ee ("s390/module: test loading modules with a lot of relocations") Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2022-02-06Merge tag 'perf_urgent_for_v5.17_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds2-2/+16
Pull perf fixes from Borislav Petkov: - Intel/PT: filters could crash the kernel - Intel: default disable the PMU for SMM, some new-ish EFI firmware has started using CPL3 and the PMU CPL filters don't discriminate against SMM, meaning that CPL3 (userspace only) events now also count EFI/SMM cycles. - Fixup for perf_event_attr::sig_data * tag 'perf_urgent_for_v5.17_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel/pt: Fix crash with stop filters in single-range mode perf: uapi: Document perf_event_attr::sig_data truncation on 32 bit architectures selftests/perf_events: Test modification of perf_event_attr::sig_data perf: Copy perf_event_attr::sig_data on modification x86/perf: Default set FREEZE_ON_SMI for all
2022-02-05Merge tag 'for-linus-5.17a-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tipLinus Torvalds4-47/+10
Pull xen fixes from Juergen Gross: - documentation fixes related to Xen - enable x2apic mode when available when running as hardware virtualized guest under Xen - cleanup and fix a corner case of vcpu enumeration when running a paravirtualized Xen guest * tag 'for-linus-5.17a-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: x86/Xen: streamline (and fix) PV CPU enumeration xen: update missing ioctl magic numers documentation Improve docs for IOCTL_GNTDEV_MAP_GRANT_REF xen: xenbus_dev.h: delete incorrect file name xen/x2apic: enable x2apic mode when supported for HVM
2022-02-05Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds17-115/+222
Pull kvm fixes from Paolo Bonzini: "ARM: - A couple of fixes when handling an exception while a SError has been delivered - Workaround for Cortex-A510's single-step erratum RISC-V: - Make CY, TM, and IR counters accessible in VU mode - Fix SBI implementation version x86: - Report deprecation of x87 features in supported CPUID - Preparation for fixing an interrupt delivery race on AMD hardware - Sparse fix All except POWER and s390: - Rework guest entry code to correctly mark noinstr areas and fix vtime' accounting (for x86, this was already mostly correct but not entirely; for ARM, MIPS and RISC-V it wasn't)" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: Use ERR_PTR_USR() to return -EFAULT as a __user pointer KVM: x86: Report deprecated x87 features in supported CPUID KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs KVM: arm64: Avoid consuming a stale esr value when SError occur RISC-V: KVM: Fix SBI implementation version RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode kvm/riscv: rework guest entry logic kvm/arm64: rework guest entry logic kvm/x86: rework guest entry logic kvm/mips: rework guest entry logic kvm: add guest_state_{enter,exit}_irqoff() KVM: x86: Move delivery of non-APICv interrupt into vendor code kvm: Move KVM_GET_XSAVE2 IOCTL definition at the end of kvm.h
2022-02-05ARM: dts: exynos: use generic node name for LPDDR3 timings in OdroidKrzysztof Kozlowski1-1/+1
The node names should have generic name, so use "timings" for LPDDR3 timings. This will also be required by dtschema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220201114749.88500-1-krzysztof.kozlowski@canonical.com
2022-02-05Merge tag 'kvmarm-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEADPaolo Bonzini1728-22055/+60790
KVM/arm64 fixes for 5.17, take #2 - A couple of fixes when handling an exception while a SError has been delivered - Workaround for Cortex-A510's single-step[ erratum
2022-02-05crypto: arm64/aes-neonbs-xts - use plain NEON for non-power-of-2 input sizesArd Biesheuvel2-108/+57
Even though the kernel's implementations of AES-XTS were updated to implement ciphertext stealing and can operate on inputs of any size larger than or equal to the AES block size, this feature is rarely used in practice. In fact, in the kernel, AES-XTS is only used to operate on 4096 or 512 byte blocks, which means that not only the ciphertext stealing is effectively dead code, the logic in the bit sliced NEON implementation to deal with fewer than 8 blocks at a time is also never used. Since the bit-sliced NEON driver already depends on the plain NEON version, which is slower but can operate on smaller data quantities more straightforwardly, let's fallback to the plain NEON implementation of XTS for any residual inputs that are not multiples of 128 bytes. This allows us to remove a lot of complicated logic that rarely gets exercised in practice. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-05crypto: arm64/aes-neonbs-ctr - fallback to plain NEON for final chunkArd Biesheuvel3-142/+55
Instead of processing the entire input with the 8-way bit sliced algorithm, which is sub-optimal for inputs that are not a multiple of 128 bytes in size, invoke the plain NEON version of CTR for the remainder of the input after processing the bulk using 128 byte strides. This allows us to greatly simplify the asm code that implements CTR, and get rid of all the branches and special code paths. It also gains us a couple of percent of performance. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-05crypto: arm/aes-neonbs-ctr - deal with non-multiples of AES block sizeArd Biesheuvel2-63/+77
Instead of falling back to C code to deal with the final bit of input that is not a round multiple of the block size, handle this in the asm code, permitting us to use overlapping loads and stores for performance, and implement the 16-byte wide XOR using a single NEON instruction. Since NEON loads and stores have a natural width of 16 bytes, we need to handle inputs of less than 16 bytes in a special way, but this rarely occurs in practice so it does not impact performance. All other input sizes can be consumed directly by the NEON asm code, although it should be noted that the core AES transform can still only process 128 bytes (8 AES blocks) at a time. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-05crypto: arm64/aes-neon-ctr - improve handling of single tail blockArd Biesheuvel2-19/+20
Instead of falling back to C code to do a memcpy of the output of the last block, handle this in the asm code directly if possible, which is the case if the entire input is longer than 16 bytes. Cc: Nathan Huckleberry <nhuck@google.com> Cc: Eric Biggers <ebiggers@google.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-05ARM: dts: ux500: Add battery thermal zones and NTCsLinus Walleij8-2/+144
Add the thermal zones and thermistors used by the battery charging code to the device tree so the charger code can look up and poll the thermal zone for battery temperature. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-04arm64: dts: qcom: sc7280: Add herobrine-r1Douglas Anderson5-2/+1647
Add the new herobrine-r1. Note that this is pretty much a re-design compared to herobrine-r0 so we don't attempt any dtsi to share stuff between them. This patch attempts to define things at 3 levels: 1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB is supposed to be the same (modulo stuffing options) across multiple boards, so trying to define what's there hopefully makes sense. NOTE that newer "CRD" boards from Qualcomm also use Qcard. When support for CRD3 is added hopefully it can use the Qcard include (and perhaps we should even evaluate it using herobrine.dtsi?) 2. The herobrine "baseboard" level. Right now most stuff is here with the exception of things that we _know_ will be different per board. We know that not all boards will have the same set of eMMC, nvme, and SD. We also know that the exact pin names are likely to be different. 3. The actual "board" level, AKA herobrine-rev1. NOTES: - This boots to command prompt. We're still waiting on the PWM driver. - This assumes LTE for now. Once it's clear how WiFi-only SKUs will work we expect some small changes. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220204140550.v4.1.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid
2022-02-04arm64: dts: qcom: Add SM8450 HDK DTSVinod Koul2-0/+406
This adds the base HDK DTS along with the usb, ufs and regulators found in this board Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220203090031.3128702-2-vkoul@kernel.org
2022-02-04arm64: dts: qcom: sc7280: Add a blank line in the dp nodeDouglas Anderson1-0/+1
It's weird that there's a blank line between the two port nodes but not between the attributes and the first port node. Add an extra blank line to make it look right. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.11.Iecb7267402e697a5cfef4cd517116ea5b308ac9e@changeid
2022-02-04arm64: dts: qcom: sc7280: Move dp_hot_plug_det pull from SoC dtsi fileDouglas Anderson3-1/+8
Pulls should be in the board files, not in the SoC dtsi file. Remove. Even though the sc7280 boards don't currently refer to dp_hot_plug_det, let's re-add the pulls there just to keep this as a no-op change. If boards don't need this / don't want it later then we can remove it from them. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.10.Id346b23642f91e16d68d75f44bcdb5b9fbd155ea@changeid
2022-02-04arm64: dts: qcom: sc7280: Move pcie1_clkreq pull / drive str to boardsDouglas Anderson3-2/+10
Pullups and drive strength don't belong in the SoC dtsi file. Move to the board file. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.8.Iffff0c12440a047212a164601e637b03b9d2fc78@changeid
2022-02-04arm64: dts: qcom: sc7280: Add edp_out port and HPD linesDouglas Anderson1-0/+13
Like dp_out, we should have defined edp_out in sc7280.dtsi so we don't need to do this in the board files. Like dp_hot_plug_det, we should define edp_hot_plug_det in sc7280.dtsi. We should set the default pinctrl for edp_hot_plug_det in sc7280.dtsi. NOTE: this is _unlike_ the dp_hot_plug_det. It is reasonable that in some boards the dedicated DP Hot Plug Detect will not be hooked up in favor of Type C mechanisms. This is unlike eDP where the Hot Plug Detect line (which functions as "panel ready" in eDP) is highly likely to be used by boards. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.7.Ic84bb69c45be2fccf50e3bd17b845fe20eec624c@changeid
2022-02-04arm64: dts: qcom: sc7280: Fix sort order of dp_hot_plug_det / pcie1_clkreq_nDouglas Anderson1-6/+6
The two nodes were mis-sorted. Reorder. This is a no-op change. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.6.I874c6f2a62b7922a33e10d390a8983219a76250b@changeid
2022-02-04arm64: dts: qcom: sc7280-idp: No need for "input-enable" on sw_ctrlDouglas Anderson1-1/+0
Specifying "input-enable" on a MSM GPIO is a no-op for the most part. The only thing it really does is to explicitly force the output of a GPIO to be disabled right at the point of a pinctrl transition. We don't need to do this and we don't typically specify "input-enable" unless there's a good reason to. Remove it. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.5.Ibaf8a803802beb089cc6266b37e6156cff3ddaec@changeid
2022-02-04arm64: dts: qcom: sc7280: Clean up sdc1 / sdc2 pinctrlDouglas Anderson3-148/+133
This patch makes a few improvements to the way that sdc1 / sdc2 pinctrl is specified on sc7280: 1. There's no reason to "group" the sdc pins into one overarching node and there's a downside: we have to replicate the hierarchy in the board device tree files. Let's clean this up. 2. There's really not a lot of reason not to list the "pinctrl" for sdc1 (eMMC) in the SoC dtsi file. These aren't GPIO pins and everyone's going to specify the same pins. 3. Even though it's likely that boards will need to override pinctrl for sdc2 (SD card) to add the card detect GPIO, we can be symmetric and add it to the SoC dsti file. 4. Let's get rid of the word "on" from the normal config and add a "sleep" suffix to the sleep config. This looks cleaner to me. This is intended to be a no-op change but it could plausibly change behavior depending on how the pinctrl code parses things. One thing to note is that "SD card detect" is explicitly listed now as keeping its pull enabled in sleep since we still want to detect card insertions even if the controller is suspended (because no card is inserted). The pinctrl framework likely did this anyway, but it's nice to see it explicit. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.4.I79baad7f52351aafb470f8b21a9fa79d7031ad6a@changeid
2022-02-04arm64: dts: qcom: sc7280: Properly sort sdc pinctrl linesDouglas Anderson1-77/+77
The sdc1 / sdc2 pinctrl lines were randomly stuffed in the middle of the qup pinctrl lines. Sort them properly. This is a no-op change. Just code movement. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.3.I6ae594129a8ad3d18af9f5ebffd895b4f6353a0a@changeid
2022-02-04arm64: dts: qcom: sc7280-herobrine: Consistently add "-regulator" suffixDouglas Anderson1-6/+6
Some of the fixed regulators were missing the "-regulator" suffix. Add it to be consistent within the file and consistent with the fixed regulators in sc7180-trogdor. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.2.I627e60c5488d54a45fd1482ca19f0f6e45192db2@changeid
2022-02-04arm64: dts: qcom: sc7180-trogdor: Add "-regulator" suffix to pp3300_hubDouglas Anderson1-1/+1
All of the other fixed regulators have the "-regulator" suffix. Add it to pp3300_hub to match. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220202132301.v3.1.I7b284531f1c992932f7eef8abaf7cc5548064f33@changeid
2022-02-04riscv/mm: Add XIP_FIXUP for riscv_pfn_basePalmer Dabbelt1-0/+1
This manifests as a crash early in boot on VexRiscv. Signed-off-by: Myrtle Shah <gatecat@ds0.me> [Palmer: split commit] Fixes: 44c922572952 ("RISC-V: enable XIP") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-02-04riscv/mm: Add XIP_FIXUP for phys_ram_basePalmer Dabbelt1-0/+1
This manifests as a crash early in boot on VexRiscv. Signed-off-by: Myrtle Shah <gatecat@ds0.me> [Palmer: split commit] Fixes: 6d7f91d914bc ("riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-02-04arm64: dts: qcom: sm8450-qrd: Enable remoteproc instancesBjorn Andersson1-0/+20
Enable the audio, compute, sensor and modem remoteproc and specify firmware path for these on the Qualcomm SM8450 QRD. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220128025513.97188-14-bjorn.andersson@linaro.org
2022-02-04arm64: dts: qcom: sm8450: Add remoteproc enablers and instancesBjorn Andersson1-0/+297
The Qualcomm SM8450 carries the familiar set of audio, compute, sensor and modem remoteprocs. Add these and their dependencies. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220128025513.97188-13-bjorn.andersson@linaro.org
2022-02-04Merge tag 'random-5.17-rc3-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/randomLinus Torvalds2-4/+4
Pull random number generator fixes from Jason Donenfeld: "For this week, we have: - A fix to make more frequent use of hwgenerator randomness, from Dominik. - More cleanups to the boot initialization sequence, from Dominik. - A fix for an old shortcoming with the ZAP ioctl, from me. - A workaround for a still unfixed Clang CFI/FullLTO compiler bug, from me. On one hand, it's a bummer to commit workarounds for experimental compiler features that have bugs. But on the other, I think this actually improves the code somewhat, independent of the bug. So a win-win" * tag 'random-5.17-rc3-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random: random: only call crng_finalize_init() for primary_crng random: access primary_pool directly rather than through pointer random: wake up /dev/random writers after zap random: continually use hwgenerator randomness lib/crypto: blake2s: avoid indirect calls to compression function for Clang CFI
2022-02-04riscv: Fix XIP_FIXUP_FLASH_OFFSETMyrtle Shah1-6/+5
There were several problems with the calculation. Not only was an 'and' being computed into t1 but thrown away; but the 'and' itself would cause problems if the granularity of the XIP physical address was less than XIP_OFFSET - in my case I had the kernel image at 2MB in SPI flash. Fixes: f9ace4ede49b ("riscv: remove .text section size limitation for XIP") Cc: stable@vger.kernel.org Signed-off-by: Myrtle Shah <gatecat@ds0.me> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-02-04lib/crypto: blake2s: avoid indirect calls to compression function for Clang CFIJason A. Donenfeld2-4/+4
blake2s_compress_generic is weakly aliased by blake2s_compress. The current harness for function selection uses a function pointer, which is ordinarily inlined and resolved at compile time. But when Clang's CFI is enabled, CFI still triggers when making an indirect call via a weak symbol. This seems like a bug in Clang's CFI, as though it's bucketing weak symbols and strong symbols differently. It also only seems to trigger when "full LTO" mode is used, rather than "thin LTO". [ 0.000000][ T0] Kernel panic - not syncing: CFI failure (target: blake2s_compress_generic+0x0/0x1444) [ 0.000000][ T0] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.16.0-mainline-06981-g076c855b846e #1 [ 0.000000][ T0] Hardware name: MT6873 (DT) [ 0.000000][ T0] Call trace: [ 0.000000][ T0] dump_backtrace+0xfc/0x1dc [ 0.000000][ T0] dump_stack_lvl+0xa8/0x11c [ 0.000000][ T0] panic+0x194/0x464 [ 0.000000][ T0] __cfi_check_fail+0x54/0x58 [ 0.000000][ T0] __cfi_slowpath_diag+0x354/0x4b0 [ 0.000000][ T0] blake2s_update+0x14c/0x178 [ 0.000000][ T0] _extract_entropy+0xf4/0x29c [ 0.000000][ T0] crng_initialize_primary+0x24/0x94 [ 0.000000][ T0] rand_initialize+0x2c/0x6c [ 0.000000][ T0] start_kernel+0x2f8/0x65c [ 0.000000][ T0] __primary_switched+0xc4/0x7be4 [ 0.000000][ T0] Rebooting in 5 seconds.. Nonetheless, the function pointer method isn't so terrific anyway, so this patch replaces it with a simple boolean, which also gets inlined away. This successfully works around the Clang bug. In general, I'm not too keen on all of the indirection involved here; it clearly does more harm than good. Hopefully the whole thing can get cleaned up down the road when lib/crypto is overhauled more comprehensively. But for now, we go with a simple bandaid. Fixes: 6048fdcc5f26 ("lib/crypto: blake2s: include as built-in") Link: https://github.com/ClangBuiltLinux/linux/issues/1567 Reported-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Tested-by: John Stultz <john.stultz@linaro.org> Acked-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-02-04riscv: eliminate unreliable __builtin_frame_address(1)Changbin Du1-4/+5
I tried different pieces of code which uses __builtin_frame_address(1) (with both gcc version 7.5.0 and 10.3.0) to verify whether it works as expected on riscv64. The result is negative. What the compiler had generated is as below: 31 fp = (unsigned long)__builtin_frame_address(1); 0xffffffff80006024 <+200>: ld s1,0(s0) It takes '0(s0)' as the address of frame 1 (caller), but the actual address should be '-16(s0)'. | ... | <-+ +-----------------+ | | return address | | | previous fp | | | saved registers | | | local variables | | $fp --> | ... | | +-----------------+ | | return address | | | previous fp --------+ | saved registers | $sp --> | local variables | +-----------------+ This leads the kernel can not dump the full stack trace on riscv. [ 7.222126][ T1] Call Trace: [ 7.222804][ T1] [<ffffffff80006058>] dump_backtrace+0x2c/0x3a This problem is not exposed on most riscv builds just because the '0(s0)' occasionally is the address frame 2 (caller's caller), if only ra and fp are stored in frame 1 (caller). | ... | <-+ +-----------------+ | | return address | | $fp --> | previous fp | | +-----------------+ | | return address | | | previous fp --------+ | saved registers | $sp --> | local variables | +-----------------+ This could be a *bug* of gcc that should be fixed. But as noted in gcc manual "Calling this function with a nonzero argument can have unpredictable effects, including crashing the calling program.", let's remove the '__builtin_frame_address(1)' in backtrace code. With this fix now it can show full stack trace: [ 10.444838][ T1] Call Trace: [ 10.446199][ T1] [<ffffffff8000606c>] dump_backtrace+0x2c/0x3a [ 10.447711][ T1] [<ffffffff800060ac>] show_stack+0x32/0x3e [ 10.448710][ T1] [<ffffffff80a005c0>] dump_stack_lvl+0x58/0x7a [ 10.449941][ T1] [<ffffffff80a005f6>] dump_stack+0x14/0x1c [ 10.450929][ T1] [<ffffffff804c04ee>] ubsan_epilogue+0x10/0x5a [ 10.451869][ T1] [<ffffffff804c092e>] __ubsan_handle_load_invalid_value+0x6c/0x78 [ 10.453049][ T1] [<ffffffff8018f834>] __pagevec_release+0x62/0x64 [ 10.455476][ T1] [<ffffffff80190830>] truncate_inode_pages_range+0x132/0x5be [ 10.456798][ T1] [<ffffffff80190ce0>] truncate_inode_pages+0x24/0x30 [ 10.457853][ T1] [<ffffffff8045bb04>] kill_bdev+0x32/0x3c ... Signed-off-by: Changbin Du <changbin.du@gmail.com> Fixes: eac2f3059e02 ("riscv: stacktrace: fix the riscv stacktrace when CONFIG_FRAME_POINTER enabled") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-02-04bpf, arm64: Enable kfunc callHou Tao1-0/+5
Since commit b2eed9b58811 ("arm64/kernel: kaslr: reduce module randomization range to 2 GB"), for arm64 whether KASLR is enabled or not, the module is placed within 2GB of the kernel region, so s32 in bpf_kfunc_desc is sufficient to represente the offset of module function relative to __bpf_call_base. The only thing needed is to override bpf_jit_supports_kfunc_call(). Signed-off-by: Hou Tao <houtao1@huawei.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20220130092917.14544-2-hotforest@gmail.com
2022-02-04ARM: dts: exynos: add charger and battery to p4noteMartin Jücker1-0/+34
Add device tree entry to support the Summit SMB347 charger which is built into the p4note devices, as well as a simple battery node. Signed-off-by: Martin Jücker <martin.juecker@gmail.com> Link: https://lore.kernel.org/r/d7f7b0f87a18b5cc44ba97390461c15469439829.1643919230.git.martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-02-04arm64: dts: ti: k3-am64-main: Add RTI watchdog nodesChristian Gmeiner2-0/+20
Add the needed bus mappings for the two main RTI memory ranges and the required device tree nodes in the main domain. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-By: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20220111134552.800704-1-christian.gmeiner@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2022-02-04KVM: x86: Use ERR_PTR_USR() to return -EFAULT as a __user pointerSean Christopherson1-3/+3
Use ERR_PTR_USR() when returning -EFAULT from kvm_get_attr_addr(), sparse complains about implicitly casting the kernel pointer from ERR_PTR() into a __user pointer. >> arch/x86/kvm/x86.c:4342:31: sparse: sparse: incorrect type in return expression (different address spaces) @@ expected void [noderef] __user * @@ got void * @@ arch/x86/kvm/x86.c:4342:31: sparse: expected void [noderef] __user * arch/x86/kvm/x86.c:4342:31: sparse: got void * >> arch/x86/kvm/x86.c:4342:31: sparse: sparse: incorrect type in return expression (different address spaces) @@ expected void [noderef] __user * @@ got void * @@ arch/x86/kvm/x86.c:4342:31: sparse: expected void [noderef] __user * arch/x86/kvm/x86.c:4342:31: sparse: got void * No functional change intended. Fixes: 56f289a8d23a ("KVM: x86: Add a helper to retrieve userspace address from kvm_device_attr") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20220202005157.2545816-1-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-04arm64: dts: meson-sm1-odroid: fix boot loop after rebootLutz Koschorreck1-1/+1
Since the correct gpio pin is used for enabling tf-io regulator the system did not boot correctly after calling reboot. [ 36.862443] reboot: Restarting system bl31 reboot reason: 0xd bl31 reboot reason: 0x0 system cmd 1. SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;CHK:1F;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0;CHK:0; bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;CHK:1F;EMMC:800;NAND:81;SD?:0;SD:400;USB:8;LOOP:1;... Setting the gpio to open drain solves the issue. Fixes: 1f80a5cf74a6 ("arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator") Signed-off-by: Lutz Koschorreck <theleks@ko-hh.de> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: reduced serial log & removed invalid character in commit message] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220128193150.GA1304381@odroid-VirtualBox
2022-02-04arm64: dts: meson-g12: drop BL32 region from SEI510/SEI610Christian Hewitt2-16/+0
The BL32/TEE reserved-memory region is now inherited from the common family dtsi (meson-g12-common) so we can drop it from board files. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220126044954.19069-4-christianshewitt@gmail.com
2022-02-04arm64: dts: meson-g12: add ATF BL32 reserved-memory regionChristian Hewitt1-0/+6
Add an additional reserved memory region for the BL32 trusted firmware present in many devices that boot from Amlogic vendor u-boot. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220126044954.19069-3-christianshewitt@gmail.com
2022-02-04arm64: dts: meson-gx: add ATF BL32 reserved-memory regionChristian Hewitt1-0/+6
Add an additional reserved memory region for the BL32 trusted firmware present in many devices that boot from Amlogic vendor u-boot. Suggested-by: Mateusz Krzak <kszaquitto@gmail.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220126044954.19069-2-christianshewitt@gmail.com
2022-02-04arm64: dts: meson-sm1-bananapi-m5: fix wrong GPIO domain for GPIOE_2Dongjin Kim1-1/+1
GPIOE_2 is in AO domain and "<&gpio GPIOE_2 ...>" changes the state of TF_PWR_EN of 'FC8731' on BPI-M5 Fixes: 976e920183e4 ("arm64: dts: meson-sm1: add Banana PI BPI-M5 board dts") Signed-off-by: Dongjin Kim <tobetter@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220127151656.GA2419733@paju
2022-02-04arm64: dts: meson-sm1-odroid: use correct enable-gpio pin for tf-io regulatorLutz Koschorreck1-1/+1
The interrupt pin of the external ethernet phy is used, instead of the enable-gpio pin of the tf-io regulator. The GPIOE_2 pin is located in the gpio_ao bank. This causes phy interrupt problems at system startup. [ 76.645190] irq 36: nobody cared (try booting with the "irqpoll" option) [ 76.649617] CPU: 0 PID: 1416 Comm: irq/36-0.0:00 Not tainted 5.16.0 #2 [ 76.649629] Hardware name: Hardkernel ODROID-HC4 (DT) [ 76.649635] Call trace: [ 76.649638] dump_backtrace+0x0/0x1c8 [ 76.649658] show_stack+0x14/0x60 [ 76.649667] dump_stack_lvl+0x64/0x7c [ 76.649676] dump_stack+0x14/0x2c [ 76.649683] __report_bad_irq+0x38/0xe8 [ 76.649695] note_interrupt+0x220/0x3a0 [ 76.649704] handle_irq_event_percpu+0x58/0x88 [ 76.649713] handle_irq_event+0x44/0xd8 [ 76.649721] handle_fasteoi_irq+0xa8/0x130 [ 76.649730] generic_handle_domain_irq+0x38/0x58 [ 76.649738] gic_handle_irq+0x9c/0xb8 [ 76.649747] call_on_irq_stack+0x28/0x38 [ 76.649755] do_interrupt_handler+0x7c/0x80 [ 76.649763] el1_interrupt+0x34/0x80 [ 76.649772] el1h_64_irq_handler+0x14/0x20 [ 76.649781] el1h_64_irq+0x74/0x78 [ 76.649788] irq_finalize_oneshot.part.56+0x68/0xf8 [ 76.649796] irq_thread_fn+0x5c/0x98 [ 76.649804] irq_thread+0x13c/0x260 [ 76.649812] kthread+0x144/0x178 [ 76.649822] ret_from_fork+0x10/0x20 [ 76.649830] handlers: [ 76.653170] [<0000000025a6cd31>] irq_default_primary_handler threaded [<0000000093580eb7>] phy_interrupt [ 76.661256] Disabling IRQ #36 Fixes: 1f80a5cf74a6 ("arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator") Signed-off-by: Lutz Koschorreck <theleks@ko-hh.de> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: removed spurious invalid & blank lines from commit message] Link: https://lore.kernel.org/r/20220127130537.GA187347@odroid-VirtualBox
2022-02-04arm64: dts: meson-g12b-odroid-n2: fix typo 'dio2133'Dongjin Kim1-2/+2
Typo in audio amplifier node, dioo2133 -> dio2133 Signed-off-by: Dongjin Kim <tobetter@gmail.com> Fixes: ef599f5f3e10 ("arm64: dts: meson: convert ODROID-N2 to dtsi") Fixes: 67d141c1f8e6 ("arm64: dts: meson: odroid-n2: add jack audio output support") Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/YfKQJejh0bfGYvof@anyang
2022-02-04KVM: x86: Report deprecated x87 features in supported CPUIDJim Mattson1-6/+7
CPUID.(EAX=7,ECX=0):EBX.FDP_EXCPTN_ONLY[bit 6] and CPUID.(EAX=7,ECX=0):EBX.ZERO_FCS_FDS[bit 13] are "defeature" bits. Unlike most of the other CPUID feature bits, these bits are clear if the features are present and set if the features are not present. These bits should be reported in KVM_GET_SUPPORTED_CPUID, because if these bits are set on hardware, they cannot be cleared in the guest CPUID. Doing so would claim guest support for a feature that the hardware doesn't support and that can't be efficiently emulated. Of course, any software (e.g WIN87EM.DLL) expecting these features to be present likely predates these CPUID feature bits and therefore doesn't know to check for them anyway. Aaron Lewis added the corresponding X86_FEATURE macros in commit cbb99c0f5887 ("x86/cpufeatures: Add FDP_EXCPTN_ONLY and ZERO_FCS_FDS"), with the intention of reporting these bits in KVM_GET_SUPPORTED_CPUID, but I was unable to find a proposed patch on the kvm list. Opportunistically reordered the CPUID_7_0_EBX capability bits from least to most significant. Cc: Aaron Lewis <aaronlewis@google.com> Signed-off-by: Jim Mattson <jmattson@google.com> Message-Id: <20220204001348.2844660-1-jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-03firmware: qcom: scm: Drop cpumask parameter from set_boot_addr()Stephan Gerhold1-2/+1
qcom_scm_set_cold/warm_boot_addr() currently take a cpumask parameter, but it's not very useful because at the end we always set the same entry address for all CPUs. This also allows speeding up probe of cpuidle-qcom-spm a bit because only one SCM call needs to be made to the TrustZone firmware, instead of one per CPU. The main reason for this change is that it allows implementing the "multi-cluster" variant of the set_boot_addr() call more easily without having to rely on functions that break in certain build configurations or that are not exported to modules. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201130505.257379-4-stephan@gerhold.net
2022-02-03Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski82-469/+1002
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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