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2022-10-18ata: ahci_qoriq: Fix compilation warningDamien Le Moal1-1/+1
When compiling with clang and W=1, the following warning is generated: drivers/ata/ahci_qoriq.c:283:22: error: cast to smaller integer type 'enum ahci_qoriq_type' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] qoriq_priv->type = (enum ahci_qoriq_type)of_id->data; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix this by using a cast to unsigned long to match the "void *" type size of of_id->data. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2022-03-07ata: Drop commas after OF match table sentinelsGeert Uytterhoeven1-1/+1
It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Add comments to clarify the purpose of the empty elements. Rewrap entries to a single line to have a consistent style. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Acked-by: Florian Fainelli <f.fainelli@gmail.com> [ahci_brcm] Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-20ata: add/use ata_taskfile::{error|status} fieldsSergey Shtylyov1-1/+1
Add the explicit error and status register fields to 'struct ata_taskfile' using the anonymous *union*s ('struct ide_taskfile' had that for ages!) and update the libata taskfile code accordingly. There should be no object code changes resulting from that... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-01-04ata: libata: add reset tracepointsHannes Reinecke1-4/+0
To follow the flow of control we should be using tracepoints, as they will tie in with the actual I/O flow and deliver a better overview about what it happening. This patch adds tracepoints for hard reset, soft reset, and postreset and adds them in the libata-eh control flow. With that we can drop the reset DPRINTK calls in the various drivers. Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2020-10-02ahci: qoriq: enable acpi support in qoriq ahci driverYuantian Tang1-3/+17
This patch enables ACPI support in qoriq ahci driver. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 45Thomas Gleixner1-5/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 11 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520170858.370933192@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-09ahci: qoriq: add ls1028a platforms supportPeng Ma1-0/+3
Ls1028a is a new introduced soc which supports ATA3.0 Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-04-09ahci: qoriq: add lx2160 platforms supportPeng Ma1-17/+35
Lx2160a is a new introduced soc which supports ATA3.0 Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2018-08-22ata: add an extra argument to ahci_platform_get_resources()Kunihiko Hayashi1-1/+1
Add an extra argument to ahci_platform_get_resources(), that is for the bitmap representing the resource to get in this function. Currently there is no resources to be defined, so all the callers set '0' to the argument. Suggested-by: Hans de Goede <hdegoede@redhat.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-04-26libahci: Allow drivers to override stop_engineEvan Wang1-1/+1
Marvell armada37xx, armada7k and armada8k share the same AHCI sata controller IP, and currently there is an issue (Errata Ref#226)that the SATA can not be detected via SATA Port-MultiPlayer(PMP). After debugging, the reason is found that the value of Port-x FIS-based Switching Control (PxFBS@0x40) became wrong. According to design, the bits[11:8, 0] of register PxFBS are cleared when Port Command and Status (0x18) bit[0] changes its value from 1 to 0, i.e. falling edge of Port Command and Status bit[0] sends PULSE that resets PxFBS bits[11:8; 0]. So it needs save the port PxFBS register before PxCMD ST write and restore the port PxFBS register afterwards in ahci_stop_engine(). This commit allows drivers to override ahci_stop_engine behavior for use by the Marvell AHCI driver(and potentially other drivers in the future). Signed-off-by: Evan Wang <xswang@marvell.com> Cc: Ofer Heifetz <oferh@marvell.com> Cc: Tejun Heo <tj@kernel.org> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-12-04ahci: qoriq: refine port register configurationYuantian Tang1-0/+12
These PP2C and PP3C registers control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively for sata port. Overwrite default values with calculated ones to get better OOB timing. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-06-02ahci: qoriq: add ls1088a platforms supportYuantian Tang1-0/+14
Ls1088a is new introduced arm-based soc with sata support with following features: * Complies with the serial ATA 3.0 specification and the AHCI 1.3.1 specification * Contains a high-speed descriptor-based DMA controller * Supports the following: * Speeds of 1.5 Gb/s (first-generation SATA), 3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA) * FIS-based switching * Native command queuing (NCQ) commands * Port multiplier operation * Asynchronous notification * SATA Vendor BIST mode Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-03-09ahci: qoriq: correct the sata ecc setting errorYuantian Tang1-2/+4
Sata ecc is controlled by only 1 bit which is 24bit in big-endian in ecc register. So only setting 24bit to disable sata ecc prevents other bits from being overwritten in ecc register. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-01-20ahci: qoriq: added ls2088a platforms supportTang Yuantian1-0/+9
Ls2088a is new introduced arm-based soc with sata support with following features: 1. Complies with the serial ATA 3.0 specification and the AHCI 1.3.1 specification 2. Contains a high-speed descriptor-based DMA controller 3. Supports the following: a. Speeds of 1.5 Gb/s (first-generation SATA), 3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA) b. FIS-based switching c. Native command queuing (NCQ) commands d. Port multiplier operation e. Asynchronous notification f. SATA BIST mode Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-01-20ahci: qoriq: report error when ecc register address is missing in dtsTang Yuantian1-2/+9
For ls1021a, and armv8 chasis 2 socs, sata ecc must be disabled. If ecc register is not found in sata node in dts, report error. This is a chip erratum described as bellow: The Read DMA operations get early termination indication from the controller. This issue is observed as CRC error in the status registers. The issue is due to address collision at address 0 in the dual port memory. The read is a dummy read to flush out the header, but due to collision the controller logs the mbit error reported by the ECC check logic. This results in the early termination of the Read DMA operation by the controller. The issue happens to all the interface speeds(GEN1/2/3) for all the products. Workaround: Disable ECC feature on those platforms. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-01-20ahci: qoriq: added a condition to enable dma coherenceTang Yuantian1-4/+11
Enable DMA coherence in SATA controller on condition that dma-coherent property exists in sata node in DTS. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-10-19ahci: qoriq: added ls1046a platform supportTang Yuantian1-3/+13
Ls1046a is a new introduced soc which supports ATA3.0. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-30ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC"Tang Yuantian1-7/+1
This reverts commit 640847298e2b7f19 ("ahci: qoriq: Disable NCQ on ls2080a SoC") The erratum has been fixed in ls2080a v2.0 and later soc. In reality, customer will not get any ls2080a v1.0 soc. Neither apply to any products. So reverting this commit won't create any side effect. Blacklisting v2.0 could also be a option, but that needs to check the soc version which is not suitable in the driver. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-08-10ahci: qoriq: enable snoopable sata read and writeTang Yuantian1-0/+6
By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-08-10ahci: qoriq: adjust sata parameterTang Yuantian1-6/+0
The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-12-16ahci: qoriq: Adjust the default register values on ls1021aTang Yuantian1-10/+14
Updated the registers' values to enhance SATA performance and reliability on ls1021a soc. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-12-16ahci: qoriq: Update the default Rx watermark valueTang Yuantian1-1/+2
The PTC[RXWM] sets the watermark value for Rx FIFO. The default value 0x20 might be insufficient for some hard drives. If the watermark value is too small, a single-cycle overflow may occur and is reported as a CRC or internal error in the PxSERR register. Updated the value to 0x29 according to the validation test. All LS platforms are affected. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-12-16ahci: qoriq: Adjust the default register values on ls1043aTang Yuantian1-0/+8
Updated the registers' values to enhance SATA performance and reliability. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-31ahci: qoriq: Disable NCQ on ls2080a SoCTang Yuantian1-1/+7
NCQ feature can't be used due to the erratum A-008473. This patch disables NCQ as a workaround. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-31ahci: qoriq: Rename LS2085A SoC support code to LS2080ATang Yuantian1-3/+3
Freescale is renaming the LS2085A SoC to LS2080A. This patch addresses the same. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-15ahci: qoriq: Fix a compiling warningArnd Bergmann1-2/+3
kbuild test robot reports the warnings: drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset': >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used >> uninitialized in this function [-Wuninitialized] drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used >> uninitialized in this function [-Wuninitialized] drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here This patch fixed it by introducing a local variable. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-09-08ahci: added a new driver for supporting Freescale AHCI sataTang Yuantian1-0/+272
Currently Freescale QorIQ series SATA is supported by ahci_platform driver. Some SoC specific settings have been put in uboot. So whether SATA works or not heavily depends on uboot. This patch will add a new driver to support QorIQ sata which removes the dependency on any other boot loader. Freescale QorIQ series sata, like ls1021a ls2085a ls1043a, is compatible with serial ATA 3.0 and AHCI 1.3 specification. Signed-off-by: Yuantian Tang <Yuantian.Tang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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