Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-01-26 | clk: aspeed: Handle inverse polarity of USB port 1 clock gate | 1 | -3/+12 | |
2018-01-26 | clk: aspeed: Fix return value check in aspeed_cc_init() | 1 | -1/+1 | |
2018-01-26 | clk: aspeed: Add reset controller | 1 | -1/+81 | |
2018-01-26 | clk: aspeed: Register gated clocks | 1 | -0/+130 | |
2018-01-26 | clk: aspeed: Add platform driver and register PLLs | 1 | -0/+130 | |
2018-01-26 | clk: aspeed: Register core clocks | 1 | -0/+177 | |
2018-01-26 | clk: Add clock driver for ASPEED BMC SoCs | 1 | -0/+141 |