Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2015-02-18 | clk: Replace explicit clk assignment with __clk_hw_set_clk | 1 | -10/+10 | |
2015-02-02 | clk: Add rate constraints to clocks | 1 | -2/+7 | |
2014-12-03 | clk: Change clk_ops->determine_rate to return a clk_hw as the best parent | 1 | -4/+5 | |
2014-07-13 | clk: composite: improve rate_hw sanity check logic | 1 | -10/+16 | |
2014-07-13 | clk: composite: allow read-only clocks | 1 | -6/+3 | |
2014-07-13 | clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent | 1 | -1/+47 | |
2014-01-15 | clk: composite: pass mux_hw into determine_rate | 1 | -1/+1 | |
2013-11-10 | clk: composite: .determine_rate support | 1 | -0/+28 | |
2013-04-12 | clk: composite: allow fixed rates & fixed dividers | 1 | -4/+13 | |
2013-04-12 | clk: composite: rename 'div' references to 'rate' | 1 | -20/+20 | |
2013-03-26 | clk: Add composite clock type | 1 | -0/+201 |