Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2013-05-29 | clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate() | 1 | -1/+1 | |
2013-04-29 | Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux | 1 | -0/+2 | |
2013-04-14 | clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate. | 1 | -0/+2 | |
2013-03-14 | clk: vt8500: Fix "fix device clock divisor calculations" | 1 | -1/+1 | |
2013-01-24 | clk: vt8500: Use common of_clk_init() function | 1 | -12/+5 | |
2013-01-15 | clk: vt8500: Add support for WM8750/WM8850 PLL clocks | 1 | -2/+100 | |
2013-01-15 | clk: vt8500: Fix division-by-0 when requested rate=0 | 1 | -2/+12 | |
2013-01-15 | clk: vt8500: Fix device clock divisor calculations | 1 | -0/+8 | |
2013-01-15 | clk: vt8500: Fix error in PLL calculations on non-exact match. | 1 | -3/+3 | |
2012-11-09 | CLK: vt8500: Fix SDMMC clk special cases | 1 | -0/+18 | |
2012-09-21 | arm: vt8500: clk: Add Common Clock Framework support | 1 | -0/+510 |