Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-11-14 | clk: hi3660: fix incorrect uart3 clock freqency | 1 | -1/+1 | |
2017-06-19 | clk: hi3660: Set PPLL2 to 2880M | 1 | -2/+2 | |
2017-06-19 | clk: hi3660: add clocks for video encoder, decoder and ISP | 1 | -0/+40 | |
2017-06-19 | clk: hi3660: fix wrong parent name of clk_mux_sysbus | 1 | -2/+4 | |
2017-06-19 | clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER | 1 | -10/+38 | |
2017-01-09 | clk: hisilicon: Add clock driver for hi3660 SoC | 1 | -0/+567 |