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path: root/drivers/clk/imx/clk-pllv3.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-06-06clk: imx7d: Fix the DDR PLL enable bitFabio Estevam1-1/+1
2017-06-01clk: imx7d: Fix the powerdown bit location of PLL DDRFabio Estevam1-0/+5
2017-01-09clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2Nikita Yushchenko1-0/+99
2016-11-01clk: imx: improve precision of AV PLL to 1 HzEmil Lundmark1-0/+8
2016-11-01clk: imx: fix integer overflow in AV PLL round rateEmil Lundmark1-2/+6
2016-06-16clk: imx: refine the powerdown bit of clk-pllv3Dong Aisheng1-10/+10
2016-06-13clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bitDong Aisheng1-4/+4
2016-06-12clk: imx: correct AV PLL rate formulaAnson Huang1-2/+6
2016-04-27clk: imx: return correct frequency for Ethernet PLLStefan Agner1-1/+8
2015-11-25clk: imx: add 'is_prepared' clk_ops callback for pllv3 clkBai Ping1-0/+14
2015-07-20clk: i.MX: Remove clk.h includeStephen Boyd1-1/+0
2015-06-03ARM: clk: imx: update pllv3 to support imx7Frank Li1-1/+8
2015-06-03ARM: imx: using unsigned variable for do_divAnson Huang1-2/+2
2015-06-03ARM: imx: move clock drivers into drivers/clkShawn Guo1-0/+331