Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-02-26 | clk: ingenic: Remove set but not used variable 'enable' | 1 | -2/+1 | |
2019-02-22 | clk: ingenic: Fix round_rate misbehaving with non-integer dividers | 1 | -5/+5 | |
2018-06-01 | clk: ingenic: Support specifying "wait for clock stable" delay | 1 | -0/+3 | |
2018-06-01 | clk: ingenic: Add support for clocks whose gate bit is inverted | 1 | -2/+3 | |
2018-01-18 | clk: ingenic: Add code to enable/disable PLLs | 1 | -15/+74 | |
2018-01-18 | clk: ingenic: support PLLs with no bypass bit | 1 | -1/+2 | |
2018-01-18 | clk: ingenic: Fix recalc_rate for clocks with fixed divider | 1 | -0/+2 | |
2017-11-03 | Update MIPS email addresses | 1 | -1/+1 | |
2016-05-12 | clk: ingenic: Allow divider value to be divided | 1 | -1/+10 | |
2015-07-20 | clk: ingenic: Include clk.h | 1 | -0/+1 | |
2015-06-21 | clk: ingenic: add driver for Ingenic SoC CGU clocks | 1 | -0/+711 |