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path: root/drivers/clk/mediatek/clk-mtk.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-09-17clk: mediatek: Register clock gate with deviceWeiyi Lu1-0/+5
2019-08-08clk: reset: Modify reset-controller driveryong.liang1-0/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-04-11clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu1-0/+1
2019-04-11clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen1-0/+2
2019-03-08Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-nextStephen Boyd1-8/+21
2019-02-26clk: mediatek: Add flags to mtk_gateJasper Mattsson1-0/+1
2019-02-26clk: mediatek: Add MUX_FLAGS macroJasper Mattsson1-2/+6
2019-02-25clk: mediatek: add MUX_GATE_FLAGS_2chunhui dai1-6/+14
2018-01-10clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being builtSean Wang1-7/+0
2017-12-26clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang1-0/+1
2017-11-02clk: mediatek: add the option for determining PLL source clockChen Zhong1-0/+1
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com1-0/+2
2016-11-08clk: mediatek: Add MT2701 clock supportShunli Wang1-5/+36
2016-05-06clk: mediatek: make dpi0_sel propagate rate changesPhilipp Zabel1-2/+13
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao1-0/+3
2015-10-01clk: mediatek: Add fixed clocks support for Mediatek SoC.James Liao1-0/+17
2015-10-01clk: mediatek: Remove unused code from MT8173.James Liao1-2/+2
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-1/+2
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao1-0/+6
2015-07-20clk: mediatek: Properly include clk.hStephen Boyd1-1/+2
2015-05-05clk: mediatek: Add reset controller supportSascha Hauer1-0/+10
2015-05-05clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao1-0/+159