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path: root/drivers/clk/meson/meson8b.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl1-13/+13
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-1/+2
2019-01-07clk: meson: meson8b: add the GPU clock treeMartin Blumenstingl1-0/+146
2019-01-07clk: meson: meson8b: use a separate clock table for Meson8Martin Blumenstingl1-6/+197
2018-12-03clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl1-8/+731
2018-12-03clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl1-0/+5
2018-12-03clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl1-1/+1
2018-11-23clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl1-0/+244
2018-11-23clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl1-10/+10
2018-11-23clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl1-6/+6
2018-11-23clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl1-0/+63
2018-11-23clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl1-0/+5
2018-11-23clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl1-1/+2
2018-11-23clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl1-2/+9
2018-11-23clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl1-1/+1
2018-11-23clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl1-7/+8
2018-11-23clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl1-9/+15
2018-09-26clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl1-7/+6
2018-09-26clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl1-60/+34
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet1-17/+17
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-73/+78
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet1-3/+0
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet1-0/+15
2018-06-09Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds1-15/+62
2018-05-21clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl1-0/+7
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet1-15/+1
2018-05-15clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl1-0/+54
2018-04-25clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl1-1/+2
2018-04-25clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl1-1/+1
2018-03-14clk: meson: Drop unused local variable and add staticStephen Boyd1-7/+6
2018-03-13clk: meson: clean-up clk81 clocksJerome Brunet1-4/+2
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet1-10/+85
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet1-3/+19
2018-03-13clk: meson: add fractional part of meson8b fixed_pllJerome Brunet1-0/+5
2018-03-13clk: meson: rework meson8b cpu clockJerome Brunet1-60/+113
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet1-21/+54
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet1-62/+87
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet1-78/+77
2018-03-13clk: meson: migrate muxes to clk_regmapJerome Brunet1-18/+9
2018-03-13clk: meson: migrate dividers to clk_regmapJerome Brunet1-15/+8
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet1-19/+20
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet1-1/+13
2018-03-13clk: meson: remove obsolete commentsJerome Brunet1-1/+0
2018-03-13clk: meson: only one loop index is necessary in probeJerome Brunet1-4/+4
2018-03-13clk: meson: use devm_of_clk_add_hw_providerJerome Brunet1-2/+2
2017-12-14clk: meson: make the spinlock naming more specificYixun Lan1-12/+12
2017-08-23Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-nextStephen Boyd1-12/+148
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl1-12/+147
2017-08-04clk: meson: meson8b: fix protection against undefined clksJerome Brunet1-0/+1
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet1-0/+5