Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-03-27 | clk: meson8b: add the mplls clocks 0, 1 and 2 | 1 | -0/+103 | |
2017-03-27 | clk: meson8b: put dividers and muxes in tables | 1 | -4/+18 | |
2017-03-27 | clk: meson: add missing const qualifiers on gate arrays | 1 | -1/+1 | |
2017-01-26 | clk: meson8b: fix clk81 register address | 1 | -1/+0 | |
2016-09-14 | clk: meson: fix CLKID_GCLK_VENCI_INT typo | 1 | -1/+1 | |
2016-09-14 | meson: clk: Use builtin_platform_driver to simplify the code | 1 | -5/+1 | |
2016-09-01 | meson: clk: Add support for clock gates | 1 | -0/+249 | |
2016-09-01 | clk: meson: Copy meson8b CLKID defines to private header file | 1 | -1/+0 | |
2016-09-01 | meson: clk: Rename register names according to Amlogic datasheet | 1 | -13/+13 | |
2016-09-01 | meson: clk: Move register definitions to meson8b.h | 1 | -16/+1 | |
2016-09-01 | clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention | 1 | -0/+447 |