aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/meson (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-12-14Merge branch 'clk-fixes' into clk-nextStephen Boyd2-0/+25
2018-12-13Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into clk-mesonStephen Boyd7-71/+870
2018-12-11clk: meson: axg-audio: use the clk input helper functionJerome Brunet1-59/+24
2018-12-05clk: meson: add clk-input helper functionJerome Brunet3-0/+50
2018-12-03clk: meson: Mark some things staticStephen Boyd2-6/+6
2018-12-03clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2-10/+782
2018-12-03clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2-0/+6
2018-12-03clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl1-1/+1
2018-11-27clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong1-1/+7
2018-11-23clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2-1/+256
2018-11-23clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2-12/+12
2018-11-23clk: meson: clk-regmap: add read-only gate opsMartin Blumenstingl2-0/+6
2018-11-23clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl1-6/+6
2018-11-23clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl1-0/+63
2018-11-23clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl1-0/+5
2018-11-23clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl1-1/+2
2018-11-23clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl1-2/+9
2018-11-23clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl1-0/+19
2018-11-23clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl1-1/+1
2018-11-23clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl1-7/+8
2018-11-23clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl1-9/+15
2018-11-23clk: meson-gxbb: Add video clocksNeil Armstrong1-0/+722
2018-11-23dt-bindings: clk: meson-gxbb: Add Video clock bindingsNeil Armstrong1-2/+24
2018-11-23clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong1-2/+49
2018-11-23clk: meson: Add vid_pll divider driverNeil Armstrong3-1/+98
2018-11-08clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet1-0/+13
2018-11-08clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt1-0/+12
2018-09-26clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl1-7/+6
2018-09-26clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl1-60/+34
2018-09-26clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan1-2/+4
2018-09-26clk: meson: axg: round audio system master clocks downJerome Brunet1-11/+23
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet5-142/+162
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet8-498/+493
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet3-8/+8
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet5-10/+113
2018-07-09clk: meson: add gen_clkJerome Brunet4-3/+135
2018-07-09clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet1-1/+0
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan2-1/+150
2018-07-09clk: meson: remove unused clk-audio-divider driverJerome Brunet3-119/+1
2018-07-09clk: meson: stop rate propagation for audio clocksJerome Brunet1-9/+7
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet4-0/+982
2018-07-09clk: meson: add axg audio sclk divider driverJerome Brunet3-1/+252
2018-07-09clk: meson: add triple phase clock driverJerome Brunet4-0/+94
2018-07-09clk: meson: add clk-phase clock driverJerome Brunet3-0/+72
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet1-9/+5
2018-07-09clk: meson: remove obsolete register accessJerome Brunet2-69/+4
2018-06-21clk: meson: audio-divider is one basedJerome Brunet1-1/+1
2018-06-19clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong1-0/+1
2018-06-09Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds20-309/+586
2018-05-21clk: meson: axg: let mpll clocks round closestJerome Brunet1-0/+4