linux-dev - Linux kernel development work

Age	Commit message (Expand)	Author	Files	Lines
2018-03-14	clk: meson: Drop unused local variable and add static	Stephen Boyd	3	-11/+10
2018-03-13	clk: meson: clean-up clk81 clocks	Jerome Brunet	2	-8/+4
2018-03-13	clk: meson: add fdiv clock gates	Jerome Brunet	6	-33/+278
2018-03-13	clk: meson: add mpll pre-divider	Jerome Brunet	6	-13/+65
2018-03-13	clk: meson: axg: add hifi pll clock	Jerome Brunet	2	-1/+56
2018-03-13	clk: meson: add ROUND_CLOSEST to the pll driver	Jerome Brunet	2	-4/+15
2018-03-13	clk: meson: add gp0 frac parameter for axg and gxl	Jerome Brunet	2	-2/+12
2018-03-13	clk: meson: improve pll driver results with frac	Jerome Brunet	2	-59/+91
2018-03-13	clk: meson: remove special gp0 lock loop	Jerome Brunet	4	-15/+1
2018-03-13	clk: meson: poke pll CNTL last	Jerome Brunet	2	-3/+3
2018-03-13	clk: meson: add fractional part of meson8b fixed_pll	Jerome Brunet	1	-0/+5
2018-03-13	clk: meson: use hhi syscon if available	Jerome Brunet	3	-24/+60
2018-03-13	clk: meson: remove obsolete cpu_clk	Jerome Brunet	3	-190/+1
2018-03-13	clk: meson: rework meson8b cpu clock	Jerome Brunet	2	-61/+119
2018-03-13	clk: meson: split divider and gate part of mpll	Jerome Brunet	8	-118/+197
2018-03-13	clk: meson: migrate plls clocks to clk_regmap	Jerome Brunet	5	-530/+535
2018-03-13	clk: meson: migrate the audio divider clock to clk_regmap	Jerome Brunet	3	-68/+30
2018-03-13	clk: meson: migrate mplls clocks to clk_regmap	Jerome Brunet	5	-354/+313
2018-03-13	clk: meson: add regmap helpers for parm	Jerome Brunet	1	-0/+16
2018-03-13	clk: meson: migrate muxes to clk_regmap	Jerome Brunet	3	-213/+184
2018-03-13	clk: meson: migrate dividers to clk_regmap	Jerome Brunet	3	-159/+142
2018-03-13	clk: meson: migrate gates to clk_regmap	Jerome Brunet	5	-195/+206
2018-03-13	clk: meson: add regmap to the clock controllers	Jerome Brunet	4	-12/+52
2018-03-13	clk: meson: remove superseded aoclk_gate_regmap	Jerome Brunet	2	-56/+0
2018-03-13	clk: meson: switch gxbb ao_clk to clk_regmap	Jerome Brunet	4	-12/+12
2018-03-13	clk: meson: add regmap clocks	Jerome Brunet	4	-0/+282
2018-03-13	clk: meson: remove obsolete comments	Jerome Brunet	3	-12/+0
2018-03-13	clk: meson: only one loop index is necessary in probe	Jerome Brunet	3	-15/+14
2018-03-13	clk: meson: use devm_of_clk_add_hw_provider	Jerome Brunet	3	-6/+7
2018-03-13	clk: meson: use dev pointer where possible	Jerome Brunet	2	-5/+5
2018-02-12	clk: meson: add axg misc bit to the mpll driver	Jerome Brunet	3	-0/+28
2018-02-12	clk: meson: axg: fix the od shift of the sys_pll	Yixun Lan	1	-1/+1
2018-02-12	clk: meson: axg: add the fractional part of the fixed_pll	Jerome Brunet	1	-0/+5
2018-02-12	clk: meson: gxbb: add the fractional part of the fixed_pll	Jerome Brunet	1	-0/+5
2018-02-12	clk: meson: fix rate calculation of plls with a fractional part	Jerome Brunet	3	-3/+15
2018-02-12	clk: meson: add the gxl hdmi pll	Jerome Brunet	1	-2/+48
2018-02-12	clk: meson: add od3 to the pll driver	Jerome Brunet	3	-3/+23
2018-02-12	clk: meson: use the frac parameter width instead of a constant	Jerome Brunet	1	-1/+1
2018-02-12	clk: meson: remove unnecessary rounding in the pll clock	Jerome Brunet	1	-8/+9
2018-02-12	clk: meson: remove useless pll rate params tables	Jerome Brunet	2	-188/+0
2018-02-12	clk: meson: check pll rate param table before using it	Jerome Brunet	1	-0/+10
2018-01-10	clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()	weiyongjun (A)	1	-0/+2
2018-01-02	Merge tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson into clk-meson	Stephen Boyd	1	-1/+1
2017-12-28	clk: meson-axg: make local symbol axg_gp0_params_table static	weiyongjun (A)	1	-1/+1
2017-12-28	clk: meson-axg: fix return value check in axg_clkc_probe()	weiyongjun (A)	1	-1/+1
2017-12-23	clk: meson: mpll: use 64-bit maths in params_from_rate	Martin Blumenstingl	1	-1/+1
2017-12-14	clk: meson-axg: add clock controller drivers	Qiufang Dai	4	-0/+1071
2017-12-14	clk: meson: make the spinlock naming more specific	Yixun Lan	3	-69/+69
2017-12-08	clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks	Jerome Brunet	1	-13/+3
2017-11-27	clk: meson: gxbb: fix wrong clock for SARADC/SANA	Yixun Lan	1	-2/+2