Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2015-03-31 | CLK: Pistachio: Register external clock gates | 1 | -0/+21 | |
2015-03-31 | CLK: Pistachio: Register system interface gate clocks | 1 | -0/+42 | |
2015-03-31 | CLK: Pistachio: Register peripheral clocks | 1 | -0/+67 | |
2015-03-31 | CLK: Pistachio: Register core clocks | 2 | -0/+200 | |
2015-03-31 | CLK: Pistachio: Add PLL driver | 3 | -0/+452 | |
2015-03-31 | CLK: Add basic infrastructure for Pistachio clocks | 3 | -0/+265 |