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path: root/drivers/clk/qcom/gcc-ipq4019.c (follow)
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2021-02-11clk: qcom: gcc-ipq4019: Remove unused variable 'ret'Lee Jones1-4/+3
Fixes the following W=1 kernel build warning(s): drivers/clk/qcom/gcc-ipq4019.c: In function ‘clk_cpu_div_set_rate’: drivers/clk/qcom/gcc-ipq4019.c:1279:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210126124540.3320214-14-lee.jones@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-9/+1
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-06clk: qcom: Move frequency table macro to common fileTaniya Das1-2/+0
Frequency table macro is used by multiple clock drivers, move frequency table macro to common header file. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2016-12-27clk: qcom: ipq4019: Add the cpu clock frequency change notifierAbhishek Sahu1-1/+39
The current driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so it the APPS clock need to be switched for stable clock during the change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> [sboyd@codeaurora.org: Indent less in probe] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add all the frequencies for apss cpuAbhishek Sahu1-2/+12
The APSS CPU clock does not contain all the frequencies in its frequency table so this patch adds the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: correct sdcc frequency and parent nameAbhishek Sahu1-2/+2
1. The parent for sdcc clock is sdccpll. 2. The frequency value was wrong so modified the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add the nodes for pcnocAbhishek Sahu1-0/+39
The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add the apss cpu pll divider clock nodeAbhishek Sahu1-0/+132
The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: remove fixed clocks and add pll clocksAbhishek Sahu1-11/+243
The current ipq4019 clock driver registered the PLL clocks and dividers as fixed clock. These fixed clock needs to be removed from driver probe function and same need to be registered with clock framework. These PLL clocks should be programmed only once and the same are being programmed already by the boot loader so the set rate operation is not required for these clocks. Only the rate can be calculated by clock operations in clock driver file so this patch adds the same. The PLL takes the reference clock from XO and generates the intermediate VCO frequency. This VCO frequency will be divided down by different PLL internal dividers. Some of the PLL internal dividers are fixed while other are programmable. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: ipq4019: changed i2c freq tableAbhishek Sahu1-2/+1
The current I2C freq table uses MND values which is not applicable for I2C since its RCG does not have MND counter. This patch updates the freq table for 19.05 MHz clk frequency with FEPLL_200 parent. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-17clk: gcc-ipq4019: Delete unnecessary assignment for the field "owner"Markus Elfring1-1/+0
The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepllMatthew McClintock1-0/+10
Drivers for these don't exist yet so we will add them as fixed clocks so we don't BUG() if we change clocks that reference these clocks. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: ipq4019: switch remaining defines to enumsMatthew McClintock1-35/+25
When this was added not all the remaining defines were switched over to use enums, so let's complete that process here Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25clk: qcom: Add IPQ4019 Global Clock Controller supportVaradarajan Narayanan1-0/+1354
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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