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2016-11-23clk: qcom: Put venus core0/1 gdscs to hw control modeSricharan R1-0/+2
The venus video ip's internal core blocks are under the control of the firmware and their powerdomains needs to be 'ON' only when used by the firmware. So putting it into hw controlled mode lets this to happen, otherwise the firmware hangs checking for this. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: gdsc: Add support for gdscs with HW controlRajendra Nayak2-0/+19
Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: clk-rpm: Fix clk_hw referencesGeorgi Djakov1-14/+22
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: clk-smd-rpm: Fix clk_hw referencesGeorgi Djakov1-14/+22
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_opsRajendra Nayak5-18/+18
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084 expects a clk_set_rate() on the sdcc rcg clk to set a floor value of supported clk rate closest to the requested rate, by looking up the frequency table. So move all the sdcc rcgs on all these platforms to use the newly introduced clk_rcg2_floor_ops Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Add rcg ops to return floor value closest to the requested rateRajendra Nayak4-9/+86
The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10Merge branch 'clk-qcom-rpm' into clk-nextStephen Boyd5-9/+1096
* clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks
2016-11-10clk: qcom: Add support for RPM ClocksGeorgi Djakov3-0/+503
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov3-0/+587
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Remove useless braces for single line if] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10clk: qcom: Always add factor clock for xo clocksGeorgi Djakov1-9/+6
Currently the RPM/RPM-SMD clock drivers do not register the xo clocks, so we should always add factor clock. When we later add xo clocks support into the drivers, we should update this function to skip registration. By doing so we avoid any DT dependencies. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10Merge branch 'clk-qcom-8994' into clk-nextStephen Boyd3-0/+2309
* clk-qcom-8994: clk: qcom: Add support for msm8994 global clock controller dt-bindings: qcom: clocks: Add msm8994 clock bindings
2016-11-10clk: qcom: Add support for msm8994 global clock controllerBastian Köcher3-0/+2309
The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by: Bastian Köcher <mail@kchr.de> [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: qcom: ipq806x: Fix board clk ratesStephen Boyd1-2/+2
The clocks on these boards run at 25 MHz, not 19.2 and 27 like other platforms. Unfortunately I copy/pasted from other similar SoCs but forgot this one is different. Fix it. Fixes: a085f877a882 ("clk: qcom: Move cxo/pxo/xo into dt files") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Add freq tables for a few rcgsRajendra Nayak1-0/+25
Add frequency tables for a few RCG clocks in msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Add .is_enabled ops for clk-alpha-pllRajendra Nayak1-0/+26
This would be useful in subsequent patches when the .set_rate operation would need to identify if the PLL is actually enabled Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Simplify return statement of is_enabled op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: Enable FSM mode for votable alpha PLLsRajendra Nayak5-28/+38
The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: handle alpha PLLs with 16bit alpha val registersRajendra Nayak2-7/+18
Some alpha PLLs have support for only a 16bit programable Alpha Value (as against the default 40bits). Add a flag to handle the 16bit alpha registers Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: Add support to initialize alpha pllsRajendra Nayak2-0/+51
Add a function to do initial configuration of the alpha plls Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: Add support for alpha pll hwfsm opsRajendra Nayak2-12/+93
Some PLLs can support an HW FSM mode (different from the Votable FSMs, though its the same bit used to enable Votable FSMs as well as HW FSMs) which enables the HW to do the bypass/reset/enable-output-ctrl sequence on its own. So all thats needed from SW is to set the FSM_ENA bit. PLL_ACTIVE_FLAG is whats used to check if the PLL is active/enabled. Some of the PLLs which support HW FSM can also need an OFFLINE request that needs to be toggled across the enable/disable. We use a flag to identify such cases and handle them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: ipq4019: changed i2c freq tableAbhishek Sahu1-2/+1
The current I2C freq table uses MND values which is not applicable for I2C since its RCG does not have MND counter. This patch updates the freq table for 19.05 MHz clk frequency with FEPLL_200 parent. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: lcc-ipq806x: Fixup overriding val in regmap_read callAxel Lin1-1/+1
Drop the assignment of regmap_read return code to val, so the code checks the value read. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: mmcc-8996: Add gpu gdscsRajendra Nayak1-0/+24
Add gpu gdsc data for msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: qcom: Handle the clamp_io assert/deassert sequenceRajendra Nayak2-1/+27
Add a flag to mark gdscs which need to support the clamp deassert/assert before and after the gdsc enable/disable Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16clk: Add USB3 PHY reset linesVivek Gautam1-0/+2
Adding missing reset lines for USB 3.0 PHY. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: gcc-msm8996: add missing pcie phy reset linesSrinivas Kandagatla1-0/+2
This patch adds missing 2 PCIE common reset lines. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: gcc-msm8996: Fix pcie 2 pipe register offsetSrinivas Kandagatla1-2/+2
This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: qcom: select GDSC for msm8996 gcc and mmccSrinivas Kandagatla1-0/+2
This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 52111672f791 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-24clk: qcom: Migrate to clk_hw based registration and OF APIsStephen Boyd6-45/+47
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: qcom: gdsc: Add the missing BIMC gdsc for msm8996Rajendra Nayak1-0/+9
Add BIMC gdsc data found in MMCC part of msm8996 family of devices. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-17clk: gcc-ipq4019: Delete unnecessary assignment for the field "owner"Markus Elfring1-1/+0
The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: qcom: Sort Makefile alphabeticallyStephen Boyd1-3/+4
We've started getting out of order, fix it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: mdm9615: Add support for MDM9615 Clock ControllersNeil Armstrong4-0/+2326
In order to support the Qualcomm MDM9615 SoC, add support for the Global and LPASS Clock Controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01clk: qcom: add EBI2 clocks to the MSM8660 GCCLinus Walleij1-0/+28
This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060 GCC. This is necessary to enable clocking of the external bus interface so that peripherals on it can be mounted. These two clocks are simple gated branch clocks. In the vendor tree clock-8x60, these clocks have some kind of dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c, what this means is undocumented, it doesn't seem like there is a parent/child relationship, so the solution I chose was to just have the EBI2 driver get and enable both clocks. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-28clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996Stephen Boyd1-16/+0
This clk is critical to operation of the SoC and should never be turned off. Furthermore, there are no consumers of this clk so let's just delete it so things like eMMC work. Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-12clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPMArchit Taneja1-32/+0
The branch clocks MMSS_MMAGIC_AXI_CLK and MMAGIC_BIMC_AXI_CLK are controlled by RPM when the APPs processor enable or disable the RPM_MMAXI_CLK. During the boot sequence, someone can enable the RPM_MMAXI_CLK, resulting in register status bits showing that these clocks are enabled, our clock driver may look at the enabled status of these clocks and try to disable them since it thinks they are unused. Don't make the clock driver touch these clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: qcom: msm8916: Fix crypto clock flagsAndy Gross1-0/+2
This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and ahb blocks. Without this flag, clk_set_rate can fail for certain frequency requests. Signed-off-by: Andy Gross <andy.gross@linaro.org> Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepllMatthew McClintock1-0/+10
Drivers for these don't exist yet so we will add them as fixed clocks so we don't BUG() if we change clocks that reference these clocks. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: ipq4019: switch remaining defines to enumsMatthew McClintock1-35/+25
When this was added not all the remaining defines were switched over to use enums, so let's complete that process here Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: Make reset_control_ops constPhilipp Zabel2-2/+2
The qcom_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04clk: qcom: Remove CLK_IS_ROOTStephen Boyd7-152/+2
This flag is a no-op now. Remove usage of the flag. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02clk: qcom: msm8960: Fix ce3_src register offsetStephen Boyd1-1/+1
The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-29clk: qcom: Fix pre-divider usage for pixel RCGArchit Taneja1-1/+3
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading its current value from the NS register. Using the pre-divider wasn't really intended when creating these ops. The pixel RCG was only intended to achieve fractional multiplication provided in the pixel_table array. Leaving the pre-divider to the existing register value results in a wrong pixel clock when the bootloader sets up the display. This was left unidentified because the IFC6410 Plus board on which this was verified didn't have a bootloader that configured the display. Don't set the RCG pre-divider in freq_tbl to the existing NS register value. Force it to 1 and only use the M/N counter to achieve the desired fractional multiplication. Cc: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25Merge branch 'clk-ipq4019' into clk-nextStephen Boyd3-0/+1363
* clk-ipq4019: clk: qcom: Add IPQ4019 Global Clock Controller support
2016-02-25clk: qcom: Add IPQ4019 Global Clock Controller supportVaradarajan Narayanan3-0/+1363
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22clk: qcom: msm8960: fix ce3_core clk enable registerSrinivas Kandagatla1-1/+1
This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-18Merge branch 'clk-fixes' into clk-nextStephen Boyd11-13/+0
* clk-fixes: clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness"
2016-02-12Revert "clk: qcom: Specify LE device endianness"Stephen Boyd11-13/+0
This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: mmcc8974: Use gdscs .parent and remove genpd callsRajendra Nayak1-13/+2
With gdsc driver capable of handling hierarchical power domains, specify oxili_gdsc as parent of oxilicx_gdsc. Remove all direct calls to genpd from the mmcc clock driver. The adding and removing of subdomains is now handled from within the gdsc driver. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak1-0/+157
Add all gdsc data which are part of mmcc on msm8996 family Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak1-0/+92
Add all data for the GDSCs which are part of msm8996 GCC block Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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