aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/qcom (follow)
AgeCommit message (Collapse)AuthorFilesLines
2022-10-27clk: qcom: Update the force mem core bit for GPU clocksTaniya Das2-0/+2
There are few GPU clocks which are powering up the memories and thus enable the FORCE_MEM_PERIPH always for these clocks to force the periph_on signal to remain active during halt state of the clock. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Fixes: 3e0f01d6c7e7 ("clk: qcom: Add graphics clock controller driver for SC7280") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Link: https://lore.kernel.org/r/1666159535-6447-1-git-send-email-quic_c_skakit@quicinc.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-14Merge branch 'clk-rate-range' into clk-nextStephen Boyd1-0/+9
- Various clk rate range fixes - Drop clk rate range constraints on clk_put() (redux) * clk-rate-range: (28 commits) clk: mediatek: clk-mux: Add .determine_rate() callback clk: tests: Add tests for notifiers clk: Update req_rate on __clk_recalc_rates() clk: tests: Add missing test case for ranges clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d clk: Introduce the clk_hw_get_rate_range function clk: Zero the clk_rate_request structure clk: Stop forwarding clk_rate_requests to the parent clk: Constify clk_has_parent() clk: Introduce clk_core_has_parent() clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock clk: Add our request boundaries in clk_core_init_rate_req clk: Introduce clk_hw_init_rate_request() clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller clk: Change clk_core_init_rate_req prototype clk: Set req_rate on reparenting clk: Take into account uncached clocks in clk_set_rate_range() clk: tests: Add some tests for orphan with multiple parents clk: tests: Add tests for mux with multiple parents clk: tests: Add tests for single parent mux ...
2022-10-14clk: qcom: gcc-msm8660: Drop hardcoded fixed board clocksLinus Walleij1-11/+0
These two clocks are now registered in the device tree as fixed clocks, causing a regression in the driver as the clock already exists with e.g. the name "pxo_board" as the MSM8660 GCC driver probes. Fix this by just not hard-coding this anymore and everything works like a charm. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: baecbda52933 ("ARM: dts: qcom: msm8660: fix node names for fixed clocks") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20221013140745.7801-1-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-04clk: qcom: gcc-sm6375: Ensure unsigned long typeStephen Boyd1-1/+1
This PLL frequency needs a UL postfix to avoid compiler warnings on 32-bit architectures. Fixes: 184fdd873d83 ("clk: qcom: Add global clock controller driver for SM6375") Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-04clk: qcom: gcc-sm6375: Remove unused variablesKonrad Dybcio1-12/+0
gcc_parent_data_15 and gcc_parent_map_15 are not used in this driver. Remove them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20221003211438.25691-1-konrad.dybcio@somainline.org Fixes: 184fdd873d83 ("clk: qcom: Add global clock controller driver for SM6375") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-03clk: qcom: kpss-xcc: convert to parent data APIChristian Marangi1-17/+9
Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. .name is changed to the legacy pxo_board following how it's declared in other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220914144743.17369-2-ansuelsmth@gmail.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-29clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-60/+60
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-4-dmitry.baryshkov@linaro.org
2022-09-29clk: qcom: gcc-msm8939: use parent_hws where possibleDmitry Baryshkov1-216/+216
Use parent_hws instead of hanving parent_data with just a single .hw entry to speed up and simplify parent lookups. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-3-dmitry.baryshkov@linaro.org
2022-09-29clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscsLuca Weiss1-1/+1
The USB controllers on sm6350 do not retain the state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928132853.179425-1-luca.weiss@fairphone.com
2022-09-29clk: qcom: gcc-sc8280xp: use retention for USB power domainsJohan Hovold1-10/+3
Since commit d399723950c4 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support) retention mode can be used on sc8280xp to maintain state during suspend instead of leaving the domain always on. This is needed to eventually allow the parent CX domain to be powered down during suspend. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220929161124.18138-1-johan+linaro@kernel.org
2022-09-29clk: qcom: gdsc: add missing error handlingJohan Hovold1-8/+17
Since commit 7eb231c337e0 ("PM / Domains: Convert pm_genpd_init() to return an error code") pm_genpd_init() can return an error which the caller must handle. The current error handling was also incomplete as the runtime PM and regulator use counts were not balanced in all error paths. Add the missing error handling to the GDSC initialisation to avoid continuing as if nothing happened on errors. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220929155816.17425-1-johan+linaro@kernel.org
2022-09-27clk: qcom: Add global clock controller driver for SM6375Konrad Dybcio3-0/+3940
Add support for the global clock controller found on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-3-konrad.dybcio@somainline.org
2022-09-27clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bitKonrad Dybcio2-2/+8
This is used on at least SM6375 and its variations. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-1-konrad.dybcio@somainline.org
2022-09-27clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscsRajendra Nayak1-2/+2
The USB controllers on sc7280 do not retain the state when the system goes into low power state and the GDSCs are turned off. This results in the controllers reinitializing and re-enumerating all the connected devices (resulting in additional delay while coming out of suspend) Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Since sc7280 only supports cx (parent of usb gdscs) Retention, there are no cxcs offsets mentioned in order to support the Retention state. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-3-quic_rjendra@quicinc.com
2022-09-27clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdscRajendra Nayak1-1/+1
The USB controller on sc7180 does not retain the state when the system goes into low power state and the GDSC is turned off. This results in the controller reinitializing and re-enumerating all the connected devices (resulting in additional delay while coming out of suspend) Fix this by updating the .pwrsts for the USB GDSC so it only transitions to retention state in low power. Since sc7180 only supports cx (parent of usb gdsc) Retention, there are no cxcs offsets mentioned in order to support the Retention state. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-2-quic_rjendra@quicinc.com
2022-09-27clk: qcom: gdsc: Fix the handling of PWRSTS_RET supportRajendra Nayak2-0/+15
GDSCs cannot be transitioned into a Retention state in SW. When either the RETAIN_MEM bit, or both the RETAIN_MEM and RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW takes care of retaining the memory/logic for the domain when the parent domain transitions to power collapse/power off state. On some platforms where the parent domains lowest power state itself is Retention, just leaving the GDSC in ON (without any RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition it to Retention. The existing logic handling the PWRSTS_RET seems to set the RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified but then explicitly turns the GDSC OFF as part of _gdsc_disable(). Fix that by leaving the GDSC in ON state. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-1-quic_rjendra@quicinc.com
2022-09-27clk: qcom: Add SC8280XP GPU clock controllerBjorn Andersson3-0/+470
Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Included kernel.h and lower-cased hex numbers] Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com
2022-09-27clk: qcom: smd: Add SM6375 clocksKonrad Dybcio1-2/+44
Add support for controlling SMD RPM clocks on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004458.151842-3-konrad.dybcio@somainline.org
2022-09-27clk: qcom: rpmhcc: add sdm670 clocksRichard Acayan1-0/+21
The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail to resolve a clock. Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7 Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920223734.151135-3-mailingradian@gmail.com
2022-09-26clk: qcom: Merge alt alpha plls for qcm2260, sm6115Iskren Chernev4-82/+57
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com
2022-09-26clk: qcom: gcc-sm6115: Move alpha pll bramo overridesIskren Chernev1-14/+12
sm6115 uses a modified default and bramo alpha pll offsets. Put them in the same place for consistency. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-3-iskren.chernev@gmail.com
2022-09-26clk: qcom: gcc-sm6115: Override default Alpha PLL regsAdam Skladowski1-16/+30
The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but currently only BRAMMO ones are overridden. Override DEFAULT ones too. A very similar thing is happening in gcc-qcm2290 driver. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Adam Skladowski <a_skl39@protonmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmail.com
2022-09-26clk: qcom: Add support for Display Clock Controller on SM8450Dmitry Baryshkov3-0/+1839
Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-4-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: alpha-pll: add support for power off mode for lucid evo PLLDmitry Baryshkov2-3/+38
PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-3-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: Add display clock controller driver for SM6115Adam Skladowski3-0/+618
Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220911164635.182973-3-a39.skl@gmail.com
2022-09-26clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSCKrishna chaitanya chundru1-1/+1
Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1663669347-29308-6-git-send-email-quic_krichai@quicinc.com
2022-09-26clk: qcom: lpass: Fix lpass audiocc probeSatya Priya1-1/+1
Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe() to avoid remapping of memory region for index 0, which is already being done through qcom_cc_map(). Fixes: 7c6a6641c2 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280") Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@baylibre.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1663673683-7018-1-git-send-email-quic_c_skakit@quicinc.com
2022-09-26clk: qcom: apss-ipq-pll: add support for IPQ8074Robert Marko1-0/+13
Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-7-robimarko@gmail.com
2022-09-26clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL configRobert Marko1-2/+6
Update the IPQ6018 Alpha PLL config to the latest one from the downstream 5.4 kernel[1]. This one should match the production SoC-s. Tested on IPQ6018 CP01-C1 reference board. [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41 Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-6-robimarko@gmail.com
2022-09-26clk: qcom: apss-ipq-pll: use OF match data for Alpha PLL configRobert Marko1-3/+9
Convert the driver to use OF match data for providing the Alpha PLL config per compatible. This is required for IPQ8074 support since it uses a different Alpha PLL config. While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make it clear that it is for IPQ6018 only. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-5-robimarko@gmail.com
2022-09-26clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as criticalRobert Marko1-1/+1
While fixing up the driver I noticed that my IPQ8074 board was hanging after CPUFreq switched the frequency during boot, WDT would eventually reset it. So mark apcs_alias0_core_clk as critical since its the clock feeding the CPU cluster and must never be disabled. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-3-robimarko@gmail.com
2022-09-26clk: qcom: apss-ipq6018: fix apcs_alias0_clk_srcRobert Marko1-7/+6
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is currently broken. More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux clock. However after debugging why it was always stuck at 800Mhz, it was figured out that its not regmap_mux compatible at all. It is a simple mux but it uses RCG2 register layout and control bits, so utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not having to provide a dummy frequency table. While we are here, use ARRAY_SIZE for number of parents. Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
2022-09-26clk: qcom: clk-rcg2: add rcg2 mux opsChristian Marangi2-0/+8
An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
2022-09-26clk: qcom: lcc-ipq806x: use ARRAY_SIZE for num_parentsChristian Marangi1-4/+4
Use ARRAY_SIZE for num_parents instead of raw number to prevent any confusion/mistake. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-4-ansuelsmth@gmail.com
2022-09-26clk: qcom: lcc-ipq806x: convert to parent dataChristian Marangi1-31/+38
Convert lcc-ipq806x driver to parent_data API. Change parent_name for pll4 to pxo_board to prepare the future to eventually drop the double pxo board clk. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-3-ansuelsmth@gmail.com
2022-09-26clk: qcom: lcc-ipq806x: add reset definitionChristian Marangi1-0/+7
Add reset definition for lcc-ipq806x. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-2-ansuelsmth@gmail.com
2022-09-26clk: qcom: cpu-8996: use constant mask for pmuxDmitry Baryshkov1-13/+6
Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-7-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: cpu-8996: don't store parents in clk_cpu_8996_pmuxDmitry Baryshkov1-13/+9
Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-6-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: cpu-8996: move ACD logic to clk_cpu_8996_pmux_determine_rateDmitry Baryshkov1-5/+2
Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-5-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: cpu-8996: declare ACD clocksDmitry Baryshkov1-12/+41
To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-4-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: cpu-8996: switch to devm_clk_notifier_registerDmitry Baryshkov1-23/+2
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-3-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocksYassine Oudjana1-32/+47
Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> [DB: switch to parent_hws for pmux clocks] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-2-dmitry.baryshkov@linaro.org
2022-09-26clk: qcom: msm8996-cpu: Convert secondary muxes to clk_regmap_muxYassine Oudjana1-32/+30
There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-5-y.oudjana@protonmail.com
2022-09-26clk: qcom: msm8996-cpu: Unify cluster orderYassine Oudjana1-18/+18
The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-4-y.oudjana@protonmail.com
2022-09-26clk: qcom: msm8996-cpu: Statically define PLL dividersYassine Oudjana1-24/+42
This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-3-y.oudjana@protonmail.com
2022-09-26clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEXYassine Oudjana1-2/+2
The parent at this index is the secondary mux, which can connect not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX to better reflect the parent. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-2-y.oudjana@protonmail.com
2022-09-15clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3dMaxime Ripard1-0/+9
The gfx3d clock is hand-crafting its own clk_rate_request in clk_gfx3d_determine_rate to pass to the parent of that clock. However, since the clk_rate_request is zero'd at creation, it will have a max_rate of 0 which will break any code depending on the clock boundaries. That includes the recent commit 948fb0969eae ("clk: Always clamp the rounded rate") which will clamp the rate given to clk_round_rate() to the current clock boundaries. For the gfx3d clock, it means that since both the min_rate and max_rate fields are set at zero, clk_round_rate() now always return 0. Let's initialize the min_rate and max_rate fields properly for that clock. Fixes: 948fb0969eae ("clk: Always clamp the rounded rate") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220816112530.1837489-25-maxime@cerno.tech Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-13clk: qcom: smd-rpm: Add clocks for MSM8909Stephan Gerhold1-1/+36
MSM8909 has mostly the same as clocks in RPM as MSM8916, but additionally the QPIC clock for the NAND flash controller. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-7-stephan.gerhold@kernkonzept.com
2022-09-13clk: qcom: gcc-msm8909: Increase delay for USB PHY resetStephan Gerhold1-1/+1
The USB PHY on MSM8909 works with the driver used on MSM8916 (phy-qcom-usb-hs.c). When turning the PHY on/off it is first reset using the standard reset controller API. On MSM8916 the reset is provided by the USB driver (ci_hdrc_msm_por_reset() in ci_hdrc_msm.c). While this seems to work on MSM8909 as well, the Qualcomm Linux sources suggest that the PHY should be reset using the GCC_USB2_HS_PHY_ONLY_BCR register instead. In general this is easy to set up in the device tree, thanks to the standard reset controller API. However, to conform to the specifications of the PHY the reset signal should be asserted for at least 10 us. This is handled correctly on MSM8916 in ci_hdrc_msm_por_reset(), but not within the GCC driver. Fix this by making use of the new "udelay" field of qcom_reset_map and set a delay of ~15 us between the assertion/deassertion of the USB PHY reset signal. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-5-stephan.gerhold@kernkonzept.com
2022-09-13clk: qcom: reset: Allow specifying custom reset delayStephan Gerhold2-1/+4
The amount of time required between asserting and deasserting the reset signal can vary depending on the involved hardware component. Sometimes 1 us might not be enough and a larger delay is necessary to conform to the specifications. Usually this is worked around in the consuming drivers, by replacing reset_control_reset() with a sequence of reset_control_assert(), waiting for a custom delay, followed by reset_control_deassert(). However, in some cases the driver making use of the reset is generic and can be used with different reset controllers. In this case the reset time requirement is better handled directly by the reset controller driver. Make this possible by adding an "udelay" field to the qcom_reset_map that allows setting a different reset delay (in microseconds). Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-4-stephan.gerhold@kernkonzept.com
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.