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2016-09-16clk: Add USB3 PHY reset linesVivek Gautam1-0/+2
Adding missing reset lines for USB 3.0 PHY. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: gcc-msm8996: add missing pcie phy reset linesSrinivas Kandagatla1-0/+2
This patch adds missing 2 PCIE common reset lines. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: gcc-msm8996: Fix pcie 2 pipe register offsetSrinivas Kandagatla1-2/+2
This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: qcom: select GDSC for msm8996 gcc and mmccSrinivas Kandagatla1-0/+2
This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 52111672f791 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-24clk: qcom: Migrate to clk_hw based registration and OF APIsStephen Boyd6-45/+47
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: qcom: gdsc: Add the missing BIMC gdsc for msm8996Rajendra Nayak1-0/+9
Add BIMC gdsc data found in MMCC part of msm8996 family of devices. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-17clk: gcc-ipq4019: Delete unnecessary assignment for the field "owner"Markus Elfring1-1/+0
The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: qcom: Sort Makefile alphabeticallyStephen Boyd1-3/+4
We've started getting out of order, fix it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: mdm9615: Add support for MDM9615 Clock ControllersNeil Armstrong4-0/+2326
In order to support the Qualcomm MDM9615 SoC, add support for the Global and LPASS Clock Controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01clk: qcom: add EBI2 clocks to the MSM8660 GCCLinus Walleij1-0/+28
This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060 GCC. This is necessary to enable clocking of the external bus interface so that peripherals on it can be mounted. These two clocks are simple gated branch clocks. In the vendor tree clock-8x60, these clocks have some kind of dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c, what this means is undocumented, it doesn't seem like there is a parent/child relationship, so the solution I chose was to just have the EBI2 driver get and enable both clocks. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-28clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996Stephen Boyd1-16/+0
This clk is critical to operation of the SoC and should never be turned off. Furthermore, there are no consumers of this clk so let's just delete it so things like eMMC work. Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-12clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPMArchit Taneja1-32/+0
The branch clocks MMSS_MMAGIC_AXI_CLK and MMAGIC_BIMC_AXI_CLK are controlled by RPM when the APPs processor enable or disable the RPM_MMAXI_CLK. During the boot sequence, someone can enable the RPM_MMAXI_CLK, resulting in register status bits showing that these clocks are enabled, our clock driver may look at the enabled status of these clocks and try to disable them since it thinks they are unused. Don't make the clock driver touch these clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: qcom: msm8916: Fix crypto clock flagsAndy Gross1-0/+2
This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and ahb blocks. Without this flag, clk_set_rate can fail for certain frequency requests. Signed-off-by: Andy Gross <andy.gross@linaro.org> Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepllMatthew McClintock1-0/+10
Drivers for these don't exist yet so we will add them as fixed clocks so we don't BUG() if we change clocks that reference these clocks. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: ipq4019: switch remaining defines to enumsMatthew McClintock1-35/+25
When this was added not all the remaining defines were switched over to use enums, so let's complete that process here Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: qcom: Make reset_control_ops constPhilipp Zabel2-2/+2
The qcom_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04clk: qcom: Remove CLK_IS_ROOTStephen Boyd7-152/+2
This flag is a no-op now. Remove usage of the flag. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02clk: qcom: msm8960: Fix ce3_src register offsetStephen Boyd1-1/+1
The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-29clk: qcom: Fix pre-divider usage for pixel RCGArchit Taneja1-1/+3
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading its current value from the NS register. Using the pre-divider wasn't really intended when creating these ops. The pixel RCG was only intended to achieve fractional multiplication provided in the pixel_table array. Leaving the pre-divider to the existing register value results in a wrong pixel clock when the bootloader sets up the display. This was left unidentified because the IFC6410 Plus board on which this was verified didn't have a bootloader that configured the display. Don't set the RCG pre-divider in freq_tbl to the existing NS register value. Force it to 1 and only use the M/N counter to achieve the desired fractional multiplication. Cc: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25Merge branch 'clk-ipq4019' into clk-nextStephen Boyd3-0/+1363
* clk-ipq4019: clk: qcom: Add IPQ4019 Global Clock Controller support
2016-02-25clk: qcom: Add IPQ4019 Global Clock Controller supportVaradarajan Narayanan3-0/+1363
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22clk: qcom: msm8960: fix ce3_core clk enable registerSrinivas Kandagatla1-1/+1
This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-18Merge branch 'clk-fixes' into clk-nextStephen Boyd11-13/+0
* clk-fixes: clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness"
2016-02-12Revert "clk: qcom: Specify LE device endianness"Stephen Boyd11-13/+0
This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: mmcc8974: Use gdscs .parent and remove genpd callsRajendra Nayak1-13/+2
With gdsc driver capable of handling hierarchical power domains, specify oxili_gdsc as parent of oxilicx_gdsc. Remove all direct calls to genpd from the mmcc clock driver. The adding and removing of subdomains is now handled from within the gdsc driver. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak1-0/+157
Add all gdsc data which are part of mmcc on msm8996 family Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak1-0/+92
Add all data for the GDSCs which are part of msm8996 GCC block Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add support for votable gdscsRajendra Nayak2-7/+26
Some gdscs might be controlled via voting registers and might not really disable when the kernel intends to disable them (due to other votes keeping them enabled) Mark these gdscs with a flag for we do not check/wait on a disable status for these gdscs within the kernel disable callback. Also at boot, if these GDSCs are found to be ON, we make sure we vote for them before we inform the genpd framework about their status. If genpd gets no users, it then disables (removes the vote) them as part of genpd_poweroff_unused() Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add support for gdscs with gds hw controllerRajendra Nayak2-17/+29
Some gdsc power domains can have a gds_hw_controller block inside to help ensure all slave devices within the power domain are idle before the gdsc is actually switched off. This is mainly useful in power domains which host a MMU, in which case its necessary to make sure there are no outstanding MMU operations or pending bus transactions before the power domain is turned off. In gdscs with gds_hw_controller block, its necessary to check the gds_hw_ctrl status bits instead of the ones in gdscr, to determine the state of the powerdomain. While at it, also move away from using jiffies and use ktime APIs instead for busy looping on status bits. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: qcom: gdsc: Add support for hierarchical power domainsRajendra Nayak3-10/+50
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs specify the parents (if any) and the driver add genpd subdomains for them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08clk: qcom: common: check for failureSudip Mukherjee1-6/+11
We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk:gcc-msm8916: add missing mss_q6_bimc_axi clockSrinivas Kandagatla1-0/+18
This clock is required for loading the qdsp firmware. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01Merge branch 'clk-msm8996' into clk-nextStephen Boyd8-0/+7159
* clk-msm8996: clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver clk: qcom: Add gfx3d ping-pong PLL frequency switching clk: qcom: Add MSM8996 Global Clock Control (GCC) driver clk: qcom: Add Alpha PLL support clk: divider: Cap table divider values to 'width' member
2015-11-30clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driverStephen Boyd3-0/+3227
Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30clk: qcom: Add gfx3d ping-pong PLL frequency switchingStephen Boyd2-0/+88
The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2, MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624 MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To make switching frequencies faster, we ping-pong between MMPLL2 and MMPLL8 when we're switching between frequencies that aren't the maximum. Implement custom rcg clk ops for this type of frequency switching. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30clk: qcom: Add MSM8996 Global Clock Control (GCC) driverStephen Boyd3-0/+3431
Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30clk: qcom: Add Alpha PLL supportStephen Boyd3-0/+413
Add support for configuring rates of, enabling, and disabling Alpha PLLs. This is sufficient for the types of PLLs found in the global and multimedia clock controllers. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-20clk: qcom: msm8916: Move xo and sleep clocks into DTGeorgi Djakov1-9/+7
Move the xo and sleep clocks to device-tree, instead of hard-coding them in the driver. This allows us to insert the RPM clocks (if they are enabled) in between the on-board oscillators and the actual clock. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-20clk: qcom: Specify LE device endiannessStephen Boyd11-0/+13
All these clock controllers are little endian devices, but so far we've been relying on the regmap mmio bus handling this for us without explicitly stating that fact. After commit 4a98da2164cf (regmap-mmio: Use native endianness for read/write, 2015-10-29), the regmap mmio bus will read/write with the __raw_*() IO accessors, instead of using the readl/writel() APIs that do proper byte swapping for little endian devices. So if we're running on a big endian processor and haven't specified the endianness explicitly in the regmap config or in DT, we're going to switch from doing little endian byte swapping to big endian accesses without byte swapping, leading to some confusing results. On my apq8074 dragonboard, this causes the device to fail to boot as we access the clock controller with big endian IO accesses even though the device is little endian. Specify the endianness explicitly so that the regmap core properly byte swaps the accesses for us. Reported-by: Kevin Hilman <khilman@linaro.org> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Cc: Simon Arlott <simon@fire.lp0.eu> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-16clk: qcom: Move cxo/pxo/xo into dt filesStephen Boyd5-43/+33
Put these clocks into the dt files instead of registering them from C code. This provides a few benefits. It allows us to specify the frequency of these clocks at the board level instead of hard-coding them in the driver. It allows us to insert an RPM clock in between the consumers of the crystals and the actual clock. And finally, it helps us transition the GCC driver to use RPM clocks when that configuration is enabled. Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-16clk: qcom: common: Add API to register board clocks backwards compatiblyStephen Boyd2-0/+91
We want to put the XO board clocks into the dt files, but we also need to be backwards compatible with an older dtb. Add an API to the common code to do this. This also makes a place for us to handle the case when the RPM clock driver is enabled and we don't want to register the fixed factor clock. Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-27clk: qcom: msm8960: Fix dsi1/2 halt bitsStephen Boyd1-2/+2
The halt bits for these clocks seem wrong. I get the following warning while booting on an msm8960-cdp: WARNING: CPU: 0 PID: 1 at drivers/clk/qcom/clk-branch.c:97 clk_branch_toggle+0xd0/0x138() dsi1_clk status stuck at 'on' Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.3.0-rc3-00113-g5532cfb567fe #110 Hardware name: Qualcomm (Flattened Device Tree) [<c0216984>] (unwind_backtrace) from [<c02138f8>] (show_stack+0x10/0x14) [<c02138f8>] (show_stack) from [<c04a525c>] (dump_stack+0x70/0xbc) [<c04a525c>] (dump_stack) from [<c0223c70>] (warn_slowpath_common+0x78/0xb4) [<c0223c70>] (warn_slowpath_common) from [<c0223d40>] (warn_slowpath_fmt+0x30/0x40) [<c0223d40>] (warn_slowpath_fmt) from [<c05fc2dc>] (clk_branch_toggle+0xd0/0x138) [<c05fc2dc>] (clk_branch_toggle) from [<c05f3f3c>] (clk_disable_unused_subtree+0x98/0x1b0) [<c05f3f3c>] (clk_disable_unused_subtree) from [<c05f3ec4>] (clk_disable_unused_subtree+0x20/0x1b0) [<c05f3ec4>] (clk_disable_unused_subtree) from [<c05f5474>] (clk_disable_unused+0x58/0xd8) [<c05f5474>] (clk_disable_unused) from [<c0209710>] (do_one_initcall+0xac/0x1ec) [<c0209710>] (do_one_initcall) from [<c0991db4>] (kernel_init_freeable+0x11c/0x1e8) [<c0991db4>] (kernel_init_freeable) from [<c0727ae0>] (kernel_init+0x8/0xec) [<c0727ae0>] (kernel_init) from [<c0210238>] (ret_from_fork+0x14/0x3c) Fix the status bits and the errors go away. Fixes: 5532cfb567fe ("clk: qcom: mmcc-8960: Add DSI related clocks") Acked-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-16clk: qcom: mmcc-8960: Add DSI related clocksArchit Taneja1-0/+404
Add rcg and branch clk structs for DSI1 and DSI2 blocks found in MSM8960 and APQ8064. Each DSI instance has 4 pairs of rcg and branch clocks. Populate arrays mmcc_msm8960_clks and mmcc_apq8064_clks with these clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-16clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGsArchit Taneja2-0/+233
DSI specific RCG clocks required customized clk_ops. There are a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL. There are a total of 2 clocks coming from the DSI PLL, which serve as inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by another divider of the PLL. In each of the 2 groups above, only one of the clocks sets its parent. These are BYTE RCG and DSI RCG for each of the groups respectively, as shown in the diagram below. The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't take in a freq table, since the DSI driver using these clocks is parent-able. The PIXEL RCG needs to derive the required pixel clock using dsixpll. It parses a m/n frac table to retrieve the correct clock. The ESC RCG doesn't have a frac M/N block, it can just apply a pre- divider. Its ops simply check if the required clock rate can be achieved by the pre-divider. +-------------------+ | |---dsixpllbyte---o---> To byte RCG | | | (sets parent rate) | | | | | | | DSI 1/2 PLL | | | | o---> To esc RCG | | (doesn't set parent rate) | | | |----dsixpll-----o---> To dsi RCG +-------------------+ | (sets parent rate) ( x = 1, 2 ) | | o---> To pixel rcg (doesn't set parent rate) Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-08clk: qcom: create virtual child device for TSENSRajendra Nayak1-1/+18
8960 family of devices have TSENS as part of GCC in hardware. Hence DT would represent a GCC node with GCC properties as well as TSENS. Create a virtual platform child device here for TSENS so the driver can probe it and use the parent (GCC) to extract DT properties. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Massaged to work with devm friendly qcom_cc_probe()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-08clk: qcom: Move gdsc config outside COMMON_CLK_QCOM configStephen Boyd1-4/+4
Having this hidden config below the COMMON_CLK_QCOM config causes menuconfig to stop indenting config items after it. <*> Support for Qualcomm's clock controllers {M} APQ8084 Global Clock Controller <M> APQ8084 Multimedia Clock Controller {M} IPQ806x Global Clock Controller <M> IPQ806x LPASS Clock Controller <M> MSM8660 Global Clock Controller <M> MSM8916 Global Clock Controller {M} APQ8064/MSM8960 Global Clock Controller <M> APQ8064/MSM8960 LPASS Clock Controller <M> MSM8960 Multimedia Clock Controller {M} MSM8974 Global Clock Controller <M> MSM8974 Multimedia Clock Controller Move it up above anything else so that we don't get odd indenting. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-08clk: qcom: Drop calls to qcom_cc_remove()Stephen Boyd13-76/+1
Now that qcom_cc_remove() is a nop, drop calls to qcom_cc_remove() and any empty driver remove functions. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-08qcom: clk: Make qcom_cc_probe() fully devm safeStephen Boyd1-11/+24
Some APIs in qcom_cc_probe() don't have a devm counterpart, so we have to use the calling device's platform data to pass pointers to the remove path. Let's use devm_add_action() instead, so that the remove path doesn't need to do anything, allowing us to remove qcom_cc_remove() entirely. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-08clk: qcom: Make oxili GDSC parent of oxili_cx GDSCStephen Boyd1-1/+10
The oxili_cx GDSC is inside the power domain of the oxili GDSC. Add the dependency so that the CX domain can properly power up. Reported-by: Rob Clark <robdclark@gmail.com> Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-17clk: qcom: Add MSM8916 audio clocksGeorgi Djakov1-0/+388
Add support for the msm8916 audio clocks. This includes core bus, low-power audio and codec clocks. They are required for audio playback. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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