linux-dev - Linux kernel development work

Age	Commit message (Expand)	Author	Files	Lines
2019-04-02	clk: renesas: rcar-gen3: Rename DRIF clocks	Takeshi Kihara	1	-8/+8
2019-04-02	clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC	Takeshi Kihara	1	-2/+2
2019-04-02	clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC	Takeshi Kihara	1	-2/+2
2019-04-02	clk: renesas: rcar-gen3: Correct parent clock of HS-USB	Kazuya Mizuguchi	1	-1/+1
2019-04-02	clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI	Kazuya Mizuguchi	1	-2/+2
2019-04-02	clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2	Simon Horman	1	-1/+1
2019-04-02	clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset	Simon Horman	1	-2/+2
2019-04-02	clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor	Takeshi Kihara	1	-2/+3
2018-12-04	clk: renesas: r8a7796: Add CPEX clock	Geert Uytterhoeven	1	-0/+1
2018-10-18	Merge branch 'clk-renesas' into clk-next	Stephen Boyd	1	-33/+34
2018-08-30	clk: renesas: use SPDX identifier for Renesas drivers	Wolfram Sang	1	-4/+1
2018-08-27	clk: renesas: r8a7796: Add OSC EXTAL predivider configuration	Geert Uytterhoeven	1	-33/+33
2018-08-27	clk: renesas: rcar-gen3: Rename rint to .r	Geert Uytterhoeven	1	-1/+2
2018-02-12	clk: renesas: r8a7796: Add Z2 clock	Takeshi Kihara	1	-0/+1
2018-02-12	clk: renesas: r8a7796: Add Z clock	Takeshi Kihara	1	-0/+1
2018-01-05	clk: renesas: r8a7796: Add FDP clock	ABE Hiroshige	1	-0/+1
2017-10-16	clk: renesas: r8a7796: Correct parent clock of INTC-AP	Geert Uytterhoeven	1	-1/+1
2017-08-17	clk: renesas: r8a7796: Add USB3.0 clock	Hiromitsu Yamasaki	1	-0/+1
2017-08-16	clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3	Geert Uytterhoeven	1	-17/+17
2017-05-15	clk: renesas: r8a7796: Add INTC-EX clock	Takeshi Kihara	1	-0/+1
2017-05-15	clk: renesas: r8a7796: Add PCIe clocks	Harunobu Kurokawa	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add PWM clock	Ryo Kodama	1	-0/+1
2017-05-15	clk: renesas: r8a7796: Add HS-USB clock	Kazuya Mizuguchi	1	-0/+1
2017-05-15	clk: renesas: r8a7796: Add Sound DVC clocks	Kazuya Mizuguchi	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add Sound SRC clock	Kazuya Mizuguchi	1	-0/+13
2017-05-15	clk: renesas: r8a7796: Add Sound SSI clock	Kazuya Mizuguchi	1	-0/+11
2017-05-15	clk: renesas: r8a7796: Add USB-DMAC clocks	Hiromitsu Yamasaki	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add Audio-DMAC clocks	Hiromitsu Yamasaki	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add EHCI/OHCI clocks	Kazuya Mizuguchi	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add HDMI clock	Koji Matsuoka	1	-0/+2
2017-03-21	clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()	Geert Uytterhoeven	1	-1/+1
2017-03-21	clk: renesas: r8a7796: Reformat core clock table	Geert Uytterhoeven	1	-6/+6
2017-03-21	clk: renesas: r8a7796: Correct name of watchdog clock	Geert Uytterhoeven	1	-1/+1
2017-03-06	clk: renesas: r8a7796: Add IMR clocks	Sergei Shtylyov	1	-0/+2
2017-01-27	clk: renesas: r8a7796: Add IIC-DVFS clock	Khiem Nguyen	1	-0/+1
2016-12-27	clk: renesas: r8a7796: Add MSIOF controller clocks	Hiromitsu Yamasaki	1	-0/+5
2016-12-27	clk: renesas: r8a7796: Add CAN FD peripheral clock	Chris Paterson	1	-0/+1
2016-12-27	clk: renesas: r8a7796: Add CANFD clock	Chris Paterson	1	-0/+1
2016-12-27	clk: renesas: r8a7796: Add CAN peripheral clock	Chris Paterson	1	-0/+2
2016-11-07	clk: renesas: r8a7796: Add VIN clocks	Niklas Söderlund	1	-0/+8
2016-11-07	clk: renesas: r8a7796: Add CSI2 clocks	Niklas Söderlund	1	-0/+4
2016-11-02	Merge branch 'rcar-rst' into clk-renesas-for-v4.10	Geert Uytterhoeven	1	-1/+7
2016-11-02	clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver	Geert Uytterhoeven	1	-1/+7
2016-11-02	clk: renesas: r8a7796: Add DU and LVDS clocks	Laurent Pinchart	1	-0/+4
2016-11-02	clk: renesas: r8a7796: Add VSP clocks	Laurent Pinchart	1	-0/+5
2016-11-02	clk: renesas: r8a7796: Add FCP clocks	Laurent Pinchart	1	-0/+8
2016-11-02	clk: renesas: r8a7796: Add DRIF clock	Ramesh Shanmugasundaram	1	-0/+8
2016-10-17	clk: renesas: r8a7796: Add I2C clocks	Ulrich Hecht	1	-0/+7
2016-10-17	clk: renesas: r8a7796: Add HSCIF clocks	Ulrich Hecht	1	-0/+5
2016-10-17	clk: renesas: r8a7796: Add SCIF clocks	Ulrich Hecht	1	-0/+5