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path: root/drivers/clk/renesas/r8a77965-cpg-mssr.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara1-8/+9
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi1-1/+1
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi1-2/+2
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman1-1/+1
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara1-1/+1
2018-12-04clk: renesas: r8a77965: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-08-28clk: renesas: r8a77965: Add FDP clockHoan Nguyen An1-0/+1
2018-08-27clk: renesas: r8a77965: Add SATA clockTakeshi Kihara1-0/+1
2018-08-27clk: renesas: r8a77965: Add OSC EXTAL predivider configurationGeert Uytterhoeven1-33/+33
2018-08-27clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven1-1/+2
2018-04-16clk: renesas: r8a77965: Add MSIOF controller clocksTakeshi Kihara1-0/+4
2018-03-13clk: renesas: r8a77965: Replace DU2 clockJacopo Mondi1-1/+1
2018-02-26clk: renesas: cpg-mssr: Add support for R-Car M3-NJacopo Mondi1-0/+334