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path: root/drivers/clk/rockchip/clk-rk3368.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-03-21clk: rockchip: support more core div settingElaine Zhang1-6/+8
2021-02-06clk: rockchip: fix DPHY gate locations on rk3368Heiko Stuebner1-2/+2
2021-02-06clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner1-1/+1
2021-02-06clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner1-2/+2
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds1-9/+3
2019-06-15clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner1-9/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-10/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd1-0/+1
2017-10-14clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCsRomain Perier1-1/+1
2017-06-02clk: rockchip: mark some special clk as critical on rk3368Elaine Zhang1-1/+4
2017-03-10clk: rockchip: mark some rk3368 core-clks as criticalElaine Zhang1-0/+3
2017-03-10clk: rockchip: export SCLK_TIMERXX id for timers on rk3368Elaine Zhang1-12/+12
2016-03-27clk: rockchip: release io resource when failing to init clkShawn Lin1-0/+1
2016-03-27clk: rockchip: Add support for multiple clock providersXing Zheng1-7/+14
2016-03-27clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng1-0/+6
2016-03-04Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-nextStephen Boyd1-37/+60
2016-02-26clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang1-37/+60
2016-02-15Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-nextMichael Turquette1-49/+33
2016-02-04clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner1-22/+6
2016-01-25clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2chzhangqing1-1/+1
2016-01-25clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8chzhangqing1-1/+1
2016-01-25clk: rockchip: rk3368: fix edp_24m parentzhangqing1-1/+1
2016-01-24clk: rockchip: rk3368: fix hdmi_cec gate-registerHeiko Stuebner1-1/+1
2016-01-24clk: rockchip: rk3368: fix parents of video encoder/decoderHeiko Stuebner1-2/+2
2016-01-24clk: rockchip: rk3368: fix cpuclk core dividersHeiko Stuebner1-20/+20
2016-01-24clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-clusterHeiko Stuebner1-1/+1
2016-01-16clk: rockchip: rk3368: fix some clock gatesJianqun xu1-13/+13
2015-12-21clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner1-1/+1
2015-12-03clk: rockchip: fix rk3368 cpuclk divider offsetsHeiko Stuebner1-2/+2
2015-12-02clk: rockchip: protect rk3368 aclk_bus and aclk_peri clocksJianqun xu1-0/+2
2015-12-02clk: rockchip: Force rk3368 PWM clock (and its parents) onCaesar Wang1-0/+5
2015-09-14clk: rockchip: add critical clock for rk3368Heiko Stübner1-0/+6
2015-07-06clk: rockchip: add rk3368 clock controllerHeiko Stuebner1-0/+881