Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-11-01 | CLK: SPEAr: make structure field and function argument as const | 1 | -2/+2 | |
2015-07-17 | Update Viresh Kumar's email address | 1 | -1/+1 | |
2012-06-20 | Viresh has moved | 1 | -1/+1 | |
2012-05-12 | SPEAr: clk: Add General Purpose Timer Synthesizer clock | 1 | -0/+17 | |
2012-05-12 | SPEAr: clk: Add Fractional Synthesizer clock | 1 | -0/+16 | |
2012-05-12 | SPEAr: clk: Add Auxiliary Synthesizer clock | 1 | -0/+43 | |
2012-05-12 | SPEAr: clk: Add VCO-PLL Synthesizer clock | 1 | -0/+58 |