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path: root/drivers/clk/sunxi-ng/ccu-sun50i-h6.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-11-05clk: sunxi-ng: h6: Set video PLLs limitsJernej Skrabec1-0/+4
2018-11-05clk: sunxi-ng: sun50i: h6: Fix MMC clock mux widthJagan Teki1-3/+3
2018-09-05clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocksIcenowy Zheng1-20/+23
2018-08-27clk: sunxi-ng: h6: fix PWM gate/reset offsetRongyi Chen1-1/+1
2018-08-27clk: sunxi-ng: h6: fix bus clocks' divider positionIcenowy Zheng1-4/+4
2018-03-21clk: sunxi-ng: add missing hdmi-slow clock for H6 CCUIcenowy Zheng1-0/+4
2018-03-18clk: sunxi-ng: add support for the Allwinner H6 CCUIcenowy Zheng1-0/+1207