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path: root/drivers/clk/sunxi-ng/ccu-sun8i-h3.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-12-04clk: sunxi-ng: h3: Allow parent change for ve clockJernej Skrabec1-1/+1
2018-12-03clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai1-1/+1
2018-08-27clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-videoJernej Skrabec1-12/+13
2018-03-02clk: sunxi-ng: h3: h5: Allow some clocks to set parent rateJernej Skrabec1-3/+6
2018-03-02clk: sunxi-ng: h3: h5: Add minimal rate for video PLLJernej Skrabec1-11/+12
2017-10-13clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLLChen-Yu Tsai1-13/+25
2017-09-17clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clockIcenowy Zheng1-1/+1
2017-09-17clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLsIcenowy Zheng1-9/+9
2017-08-23Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-nextStephen Boyd1-1/+12
2017-08-04clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3Icenowy Zheng1-1/+1
2017-08-04clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai1-0/+11
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring1-2/+1
2017-06-07clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai1-5/+5
2017-03-06clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng1-7/+320
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman1-0/+10
2016-11-11clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai1-5/+5
2016-09-14Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-nextStephen Boyd1-5/+5
2016-08-29clk: sunxi-ng: Fix wrong reset register offsetsJorik Jonker1-8/+8
2016-08-25clk: sunxi-ng: mux: support fixed pre-dividers on multiple parentsChen-Yu Tsai1-5/+5
2016-07-11clk: sunxi-ng: h3: Fix audio clock divider offsetMaxime Ripard1-2/+2
2016-07-08clk: sunxi-ng: Add H3 clocksMaxime Ripard1-0/+826