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path: root/drivers/clk/tegra/clk-tegra30.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-111/+2
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6
2016-04-28clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach1-0/+1
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang1-1/+1
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein1-110/+117
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein1-9/+15
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-1/+1
2015-11-18clk: tegra: Format tables consistentlyThierry Reding1-189/+189
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding1-10/+5
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding1-1/+1
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein1-1/+7
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-1/+0
2015-05-13clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler1-1/+1
2015-04-10clk: tegra: Model oscillator as clockThierry Reding1-1/+2
2015-04-10clk: tegra: Use consistent indentationThierry Reding1-10/+10
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-1/+6
2014-07-17ARM: tegra: Convert PMC to a driverThierry Reding1-1/+1
2014-07-17ARM: tegra: Move includes to include/soc/tegraThierry Reding1-1/+4
2013-12-11clk: tegra: remove bogus PCIE_XCLKStephen Warren1-7/+0
2013-12-11clk: tegra: implement a reset driverStephen Warren1-1/+2
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot1-1/+1
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding1-1/+3
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding1-0/+1
2013-11-26clk: tegra: move tegra30 to common infraPeter De Schrijver1-895/+403
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-2/+2
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver1-27/+35
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver1-28/+11
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver1-201/+116
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver1-9/+10
2013-08-28clk: tegra30: Don't wait for PLL_U lock bitTuomas Tynkkynen1-1/+1
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan1-11/+22
2013-08-08clk: tegra30: Fix incorrect placement of __initdataSachin Kamat1-1/+1
2013-07-03Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds1-3/+22
2013-06-16ARM: tegra30: clocks: Fix pciex clock registrationJay Agarwal1-5/+6
2013-06-11clk: tegra: override bits for Tegra30 PLLMPeter De Schrijver1-0/+18
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad1-1/+2
2013-05-31clk: tegra: fix clk_out parents listPrashant Gaikwad1-2/+2
2013-05-04Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-131/+145
2013-04-09Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatformArnd Bergmann1-2/+1
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver1-1/+1
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver1-11/+11
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver1-0/+7
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver1-117/+117
2013-04-04clk: tegra: defer application of init tableStephen Warren1-1/+6
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad1-1/+1
2013-04-04clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding1-0/+2
2013-03-29ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>Stephen Warren1-2/+1
2013-03-04clk: Tegra: Remove duplicate smp_twd clockPrashant Gaikwad1-1/+0
2013-02-13clk: tegra: initialise parent of uart clocksLaxman Dewangan1-1/+5