Age | Commit message (Expand) | Author | Files | Lines |
2018-10-16 | clk: tegra210: Include size.h for compilation ease | ![](https://seccdn.libravatar.org/avatar/8c6b7eae8dbc6e6ed2f41596b1254753?s=13&d=retro) Stephen Boyd | 1 | -0/+1 |
2018-10-16 | clk: tegra: Fixes for MBIST work around | ![](https://seccdn.libravatar.org/avatar/d723f45badf79e6c63076882b6db9a4f?s=13&d=retro) Joseph Lo | 1 | -3/+3 |
2018-10-16 | clk: tegra: probe deferral error reporting | ![](https://seccdn.libravatar.org/avatar/4ab181c51cee57f9aa62a078e7dc78f4?s=13&d=retro) Marcel Ziswiler | 1 | -2/+6 |
2018-08-14 | Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next | ![](https://seccdn.libravatar.org/avatar/8c6b7eae8dbc6e6ed2f41596b1254753?s=13&d=retro) Stephen Boyd | 8 | -40/+343 |
2018-08-14 | Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next | ![](https://seccdn.libravatar.org/avatar/8c6b7eae8dbc6e6ed2f41596b1254753?s=13&d=retro) Stephen Boyd | 4 | -7/+15 |
2018-07-25 | clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De-Schrijver | 3 | -15/+12 |
2018-07-25 | clk: tegra: Add sdmmc mux divider clock | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De-Schrijver | 3 | -0/+278 |
2018-07-25 | clk: tegra: Refactor fractional divider calculation | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De Schrijver | 4 | -25/+52 |
2018-07-25 | clk: tegra: Fix includes required by fence_udelay() | ![](https://seccdn.libravatar.org/avatar/28aebcbca58ef758bb4cb99eb1445197?s=13&d=retro) Aapo Vienamo | 1 | -0/+1 |
2018-07-08 | clk: tegra: emc: Avoid out-of-bounds bug | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -1/+1 |
2018-07-08 | clk: tegra: Mark Memory Controller clock as critical | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -2/+3 |
2018-07-08 | clk: tegra: Make vde a child of pll_c3 | ![](https://seccdn.libravatar.org/avatar/03bddb20d4030f1f862c9d4a07956621?s=13&d=retro) Thierry Reding | 1 | -1/+1 |
2018-07-08 | clk: tegra: Make vic03 a child of pll_c3 | ![](https://seccdn.libravatar.org/avatar/03bddb20d4030f1f862c9d4a07956621?s=13&d=retro) Thierry Reding | 1 | -0/+1 |
2018-07-08 | clk: tegra: bpmp: Don't crash when a clock fails to register | ![](https://seccdn.libravatar.org/avatar/c5aae0d4d408732e9b27b59e38f780d2?s=13&d=retro) Mikko Perttunen | 1 | -3/+9 |
2018-06-12 | treewide: kzalloc() -> kcalloc() | ![](https://seccdn.libravatar.org/avatar/1b45cc190ad060a47c5518963894c4c0?s=13&d=retro) Kees Cook | 1 | -3/+4 |
2018-06-04 | Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and 'clk-debugfs-simple' into clk-next | ![](https://seccdn.libravatar.org/avatar/8c6b7eae8dbc6e6ed2f41596b1254753?s=13&d=retro) Stephen Boyd | 1 | -31/+11 |
2018-06-01 | clk: tegra: no need to check return value of debugfs_create functions | ![](https://seccdn.libravatar.org/avatar/cbd18395260b6be2575187286a262f9a?s=13&d=retro) Greg Kroah-Hartman | 1 | -31/+11 |
2018-05-18 | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 7 | -8/+39 |
2018-05-18 | clk: tegra20: Correct parents of CDEV1/2 clocks | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -4/+2 |
2018-05-18 | clk: tegra20: Add DEV1/DEV2 OSC dividers | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -0/+14 |
2018-03-12 | clk: tegra: Fix pll_u rate configuration | ![](https://seccdn.libravatar.org/avatar/750e78e5f4bf9ace5d0cb8d3fc359dbd?s=13&d=retro) Marcel Ziswiler | 1 | -0/+2 |
2018-03-12 | clk: tegra: Specify VDE clock rate | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 4 | -1/+4 |
2018-03-12 | clk: tegra20: Correct PLL_C_OUT1 setup | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -3/+3 |
2018-03-12 | clk: tegra: Mark HCLK, SCLK and EMC as critical | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 8 | -36/+26 |
2018-03-08 | clk: tegra: MBIST work around for Tegra210 | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De Schrijver | 1 | -2/+342 |
2018-03-08 | clk: tegra: add fence_delay for clock registers | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De Schrijver | 1 | -0/+7 |
2018-03-08 | clk: tegra: Add la clock for Tegra210 | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De Schrijver | 1 | -0/+14 |
2017-11-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux | ![](https://seccdn.libravatar.org/avatar/fb47627bc8c0bcdb36321edfbf02e916?s=13&d=retro) Linus Torvalds | 13 | -66/+102 |
2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | ![](https://seccdn.libravatar.org/avatar/cbd18395260b6be2575187286a262f9a?s=13&d=retro) Greg Kroah-Hartman | 2 | -0/+2 |
2017-11-01 | clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() | ![](https://seccdn.libravatar.org/avatar/f606eae2e3451996df5c7604a199107c?s=13&d=retro) Nicolin Chen | 1 | -2/+2 |
2017-11-01 | clk: tegra: dfll: Fix drvdata overwriting issue | ![](https://seccdn.libravatar.org/avatar/f606eae2e3451996df5c7604a199107c?s=13&d=retro) Nicolin Chen | 3 | -13/+11 |
2017-11-01 | clk: tegra: Fix cclk_lp divisor register | ![](https://seccdn.libravatar.org/avatar/32b3f613f9e074afffbd0c43380d11cc?s=13&d=retro) Michał Mirosław | 1 | -1/+1 |
2017-11-01 | clk: tegra: Bump SCLK clock rate to 216 MHz | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -1/+1 |
2017-11-01 | clk: tegra: Use common definition of APBDMA clock gate | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -5/+1 |
2017-11-01 | clk: tegra: Correct parent of the APBDMA clock | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 1 | -1/+1 |
2017-11-01 | clk: tegra: Add AHB DMA clock entry | ![](https://seccdn.libravatar.org/avatar/38f8ab512cdd3849b7df36e9ddcfb0db?s=13&d=retro) Dmitry Osipenko | 4 | -0/+4 |
2017-11-01 | clk: tegra: Mark APB clock as critical | ![](https://seccdn.libravatar.org/avatar/888d04fd6b3cdbcf55f91a3f94aa5471?s=13&d=retro) Jon Hunter | 1 | -1/+1 |
2017-10-19 | clk: tegra: Make tegra_clk_pll_params __ro_after_init | ![](https://seccdn.libravatar.org/avatar/c3ef72c9b31a87b949f0f9800b5ef11f?s=13&d=retro) Bhumika Goyal | 1 | -8/+8 |
2017-10-19 | clk: tegra: Fix sor1_out clock implementation | ![](https://seccdn.libravatar.org/avatar/03bddb20d4030f1f862c9d4a07956621?s=13&d=retro) Thierry Reding | 2 | -16/+47 |
2017-10-19 | clk: tegra: Use tegra_clk_register_periph_data() | ![](https://seccdn.libravatar.org/avatar/03bddb20d4030f1f862c9d4a07956621?s=13&d=retro) Thierry Reding | 4 | -13/+4 |
2017-10-19 | clk: tegra: Add peripheral clock registration helper | ![](https://seccdn.libravatar.org/avatar/03bddb20d4030f1f862c9d4a07956621?s=13&d=retro) Thierry Reding | 2 | -0/+11 |
2017-10-19 | clk: tegra: Check BPMP response return code | ![](https://seccdn.libravatar.org/avatar/3e4400c842a8e673c45b8b38cfdcd1e9?s=13&d=retro) Timo Alho | 1 | -5/+10 |
2017-08-23 | clk: tegra: Fix Tegra210 PLLU initialization | ![](https://seccdn.libravatar.org/avatar/df6bd845e6477448685dd6fa2577682f?s=13&d=retro) Alex Frid | 1 | -2/+4 |
2017-08-23 | clk: tegra: Correct Tegra210 UTMIPLL poweron delay | ![](https://seccdn.libravatar.org/avatar/df6bd845e6477448685dd6fa2577682f?s=13&d=retro) Alex Frid | 1 | -3/+3 |
2017-08-23 | clk: tegra: Fix T210 PLLRE registration | ![](https://seccdn.libravatar.org/avatar/df6bd845e6477448685dd6fa2577682f?s=13&d=retro) Alex Frid | 1 | -20/+1 |
2017-08-23 | clk: tegra: Update T210 PLLSS (D2/DP) registration | ![](https://seccdn.libravatar.org/avatar/df6bd845e6477448685dd6fa2577682f?s=13&d=retro) Alex Frid | 1 | -39/+9 |
2017-08-23 | clk: tegra: Re-factor T210 PLLX registration | ![](https://seccdn.libravatar.org/avatar/df6bd845e6477448685dd6fa2577682f?s=13&d=retro) Alex Frid | 4 | -49/+10 |
2017-08-23 | clk: tegra: don't warn for pll_d2 defaults unnecessarily | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De Schrijver | 1 | -2/+4 |
2017-08-23 | clk: tegra: change post IDDQ release delay to 5us | ![](https://seccdn.libravatar.org/avatar/255692fc72913bbf4e64ea605327c822?s=13&d=retro) Peter De Schrijver | 1 | -1/+1 |
2017-08-23 | clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C | ![](https://seccdn.libravatar.org/avatar/df6bd845e6477448685dd6fa2577682f?s=13&d=retro) Alex Frid | 1 | -1/+2 |