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path: root/drivers/clk/ti/dpll.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-04-21clk: ti: fix linker error with !SOC_OMAP4Arnd Bergmann1-2/+6
2017-03-08clk: ti: convert to use proper register definition for all accessesTero Kristo1-30/+18
2017-03-08clk: ti: dpll44xx: fix clksel register initializationTero Kristo1-0/+15
2017-03-08clk: ti: drop unnecessary MEMMAP_ADDRESSING flagTero Kristo1-2/+0
2017-03-08clk: ti: use automatic clock alias generation frameworkTero Kristo1-3/+3
2016-12-08clk: ti: omap36xx: Work around sprz319 advisory 2.1Richard Watts1-1/+18
2016-04-15clk: ti: amx3xx: limit the maximum frequency of DPLLs based on specTero Kristo1-0/+5
2016-02-26clk: ti: Update for of_clk_get_parent_count() returning unsigned intStephen Boyd1-1/+1
2016-02-22clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrsTero Kristo1-6/+19
2015-08-24clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd1-2/+2
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-0/+1
2015-07-28clk: ti: make use of of_clk_parent_fill helper functionDinh Nguyen1-3/+1
2015-07-20clk: ti: Include clk.hStephen Boyd1-0/+1
2015-05-14clk: ti: Silence sparse warningsStephen Boyd1-1/+1
2015-03-24clk: ti: fix ti_clk_get_reg_addr error handlingTero Kristo1-3/+3
2015-02-03clk: omap: compile legacy omap3 clocks conditionallyArnd Bergmann1-0/+2
2015-01-30clk: ti: dpll: add support for legacy DPLL initTero Kristo1-11/+108
2014-11-13ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()Tero Kristo1-0/+15
2014-07-01clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabledRoger Quadros1-2/+3
2014-06-06CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequenciesNishanth Menon1-0/+21
2014-05-28CLK: TI: DPLL: add support for omap2 core dpllTero Kristo1-11/+67
2014-05-28CLK: TI: DPLL: simplify autoidle register detection logicTero Kristo1-24/+15
2014-01-17CLK: TI: Add DPLL clock supportTero Kristo1-0/+558
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