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2018-03-23clk: rockchip: Fix wrong parents for MMC phase clock for rk3328Shawn Lin1-8/+8
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") catches some gremlins for clk-rk3328.c that the parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not sclk_{sdmmc, sdio, emmc}. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-23clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin1-1/+1
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") catches one gremlin again for clk-rk3228.c that the parent of SDMMC phase clock should be sclk_sdmmc0, but not sclk_sdmmc. However, the naming of the sdmmc clocks varies in the manual with the card clock having the 0 while the hclk is named without appended 0. So standardize one one format to prevent confusion, as there also is only one (non-sdio) mmc controller on the soc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-21clk: renesas: cpg-mssr: Adjust r8a77980 ifdefMagnus Damm1-1/+1
Adjust the R8A77980-specific #ifdefs to use CLK instead of ARCH to follow same style as other SoCs. Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support") Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21clk: renesas: rcar-gen3: Always use readl()/writel()Geert Uytterhoeven1-7/+7
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: sh73a0: Always use readl()/writel()Geert Uytterhoeven1-7/+7
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: rza1: Always use readl()/writel()Geert Uytterhoeven1-2/+2
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: rcar-gen2: Always use readl()/writel()Geert Uytterhoeven1-9/+8
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: r8a7740: Always use readl()/writel()Geert Uytterhoeven1-4/+4
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: r8a73a4: Always use readl()/writel()Geert Uytterhoeven1-6/+5
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: mstp: Always use readl()/writel()Geert Uytterhoeven1-2/+2
On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: renesas: div6: Always use readl()/writel()Geert Uytterhoeven1-11/+11
On arm32/arm64, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21clk: sunxi-ng: add missing hdmi-slow clock for H6 CCUIcenowy Zheng2-1/+5
The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-20clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()Wei Yongjun1-0/+2
platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Fixes: 322269163a36 ("clk: hisilicon: add hisi_clk_alloc function.") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: cfgchip: Add TI DA8XX USB PHY clocksDavid Lechner1-0/+351
This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes place during the clk_enable() callback. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: New driver for TI DA8XX CFGCHIP clocksDavid Lechner2-0/+441
This adds a new driver for the gate and multiplexer clocks in the CFGCHIPn syscon registers on TI DA8XX-type SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM646x PSCDavid Lechner4-0/+83
This adds platform-specific declarations for the PSC clocks on TI DM646x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM644x PSCDavid Lechner4-0/+86
This adds platform-specific declarations for the PSC clocks on TI DM644x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM365 PSCDavid Lechner4-0/+99
This adds platform-specific declarations for the PSC clocks on TI DM365 based systems. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM355 PSCDavid Lechner4-0/+91
This adds platform-specific declarations for the PSC clocks on TI DM355 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DA850 PSCDavid Lechner4-0/+158
This adds platform-specific declarations for the PSC clocks on TI DA850/ OMAP-L138/AM18XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DA830 PSCDavid Lechner4-0/+122
This adds platform-specific declarations for the PSC clocks on TI DA830/ OMAP-L137/AM17XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: New driver for davinci PSC clocksDavid Lechner3-0/+641
This adds a new driver for mach-davinci PSC clocks. This is porting the code from arch/arm/mach-davinci/psc.c to the common clock framework and is converting it to use regmap to simplify the code. Additionally, it adds device tree support for these clocks. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the keystone driver makes the assumption that there is only one PSC per SoC and uses global variables, but here we have two controllers per SoC. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM646x PLLDavid Lechner4-0/+90
This adds platform-specific declarations for the PLL clocks on TI DM646x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM644x PLLDavid Lechner4-0/+86
This adds platform-specific declarations for the PLL clocks on TI DM644x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM365 PLLDavid Lechner4-0/+151
This adds platform-specific declarations for the PLL clocks on TI DM365 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DM355 PLLDavid Lechner4-0/+85
This adds platform-specific declarations for the PLL clocks on TI DM355 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DA850 PLLDavid Lechner4-0/+222
This adds platform-specific declarations for the PLL clocks on TI DA850/ OMAP-L138/AM18XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: Add platform information for TI DA830 PLLDavid Lechner4-0/+76
This adds platform-specific declarations for the PLL clocks on TI DA830/ OMAP-L137/AM17XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: davinci: New driver for davinci PLL clocksDavid Lechner4-0/+1014
This adds a new driver for mach-davinci PLL clocks. This is porting the code from arch/arm/mach-davinci/clock.c to the common clock framework. Additionally, it adds device tree support for these clocks. The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent compile errors until the clock code in arch/arm/mach-davinci is removed. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the register layouts are a bit different, which would add even more if/else mess to the keystone clocks. And the keystone PLL driver doesn't support setting clock rates. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_removeSudeep Holla1-10/+2
Commit aa795c41d9cd ("clk: Add devm_of_clk_add_hw_provider()/del_provider() APIs") adds devm_of_clk_add_hw_provider which takes care of deleting the clock provider when the clock providers device is removed. This patch makes use of devm_of_clk_add_hw_provider() instead of of_clk_add_hw_provider() so that we can eliminate the need of explicit scmi_clocks_remove for just doing of_clk_del_provider() Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2018-03-20clk: mediatek: add audsys support for MT2701Ryder Lee3-0/+193
Add clock driver support for MT2701 audsys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: mediatek: add devm_of_platform_populate() for MT7622 audsysRyder Lee1-1/+13
Add devm_of_platform_populate() to populate devices which are children of the root node. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: qcom: rpmcc: Add support to XO buffered clocksSrinivas Kandagatla1-1/+78
XO is onchip buffer clock to generate 19.2MHz. This patch adds support to 5 XO buffer clocks found on PMIC8921, these buffer clocks can be controlled from external pin or in manual mode. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: mediatek: update clock driver of MT2712Weiyi Lu1-14/+55
According to ECO design change, 1. add new clock mux data and change some 2. add new clock gate data and clock factor data 3. change status register offset of infra subsystem Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: lpc32xx: Set name of regmap_configJeffy Chen1-0/+1
We are now allowing to register debugfs without a valid device, and not having a valid name will end up using "dummy*" to create debugfs dir. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: Don't show the incorrect clock phaseShawn Lin1-0/+3
It's found that the clock phase output from clk_summary is wrong compared to the actual phase reading from the register. cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample sdio_sample 0 1 0 50000000 0 -22 It exposes an issue that clk core, clk_core_get_phase, always returns the cached core->phase which should be either updated by calling clk_set_phase or directly from the first place the clk was registered. When registering the clk, the core->phase geting from ->get_phase() may return negative value indicating error. This is quite common since the clk's phase may be highly related to its parent chain, but it was temporarily orphan when registered, since its parent chains hadn't be ready at that time, so the clk drivers decide to return error in this case. However, if no clk_set_phase is called or maybe the ->set_phase() isn't even implemented, the core->phase would never be updated. This is wrong, and we should try to update it when all its parent chains are settled down, like the way of updating clock rate for that. But it's not deserved to complicate the code now and just update it anyway when calling clk_core_get_phase, which would be much simple and enough. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: mvebu: armada-38x: add support for missing clocksRichard Genoud1-7/+7
Clearfog boards can come with a CPU clocked at 1600MHz (commercial) or 1333MHz (industrial). They have also some dip-switches to select a different clock (666, 800, 1066, 1200). The funny thing is that the recovery button is on the MPP34 fq selector. So, when booting an industrial board with this button down, the frequency 666MHz is selected (and the kernel didn't boot). This patch add all the missing clocks. The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ). Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385") Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants Cc: <stable@vger.kernel.org> # 3.16.x Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: clk-gpio: Allow GPIO to sleep in set/get_parentMike Looijmans1-2/+2
When changing or retrieving clock parents, the caller is in a sleepable state (like prepare) so the GPIO operation need not be atomic. Replace gpiod_{g|s}et_value with gpiod_{g|s}et_value_cansleep in the {g|s}et_parent calls for the GPIO based clock mux. This fixes a "slowpath" warning when the GPIO controller is an I2C expander or something similar. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: enable hi655x common clk automaticallyRiku Voipio1-2/+4
Without COMMON_CLK_HI655X Wifi and bluetooth are non-functional on Hikey. As suggested by Arnd, enable the driver automatically when the parent driver is selected. With sensible defaults in place, we can leave other choices for EXPERT. Cc: John Stultz <john.stultz@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Suggested-by: Arnd Bergmann <arnd@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: stm32: add configuration flags for each of the stm32 driversBenjamin Gaignard2-2/+16
Add two configuration flags to be able to not compile all the time stm32f and stm32h7 drivers when ARCH_STM32 is set. That help to save some space on those small platforms. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: stm32: Add clk entry for SDMMC2 on stm32F769Patrice Chotard1-1/+2
STM32F769 has 2 SDMMC port, add clock entry for the second one. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: stm32: Add DSI clock for STM32F469 BoardGabriel Fernandez1-1/+10
This patch adds DSI clock for STM32F469 board Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: uniphier: add Pro4/Pro5/PXs2 audio system clockKatsuhiro Suzuki1-0/+11
Add clock for audio subsystem (AIO) on UniPhier Pro4/Pro5/PXs2 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: mediatek: update missing clock data for MT7622 audsysRyder Lee1-0/+1
Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang1-7/+8
The clock for which all PWM devices on MT7623 or MT2701 actually depending on has to be divided by four from its parent clock axi_sel in the clock path prior to PWM devices. Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of clock axi_sel allows that PWM devices can have the correct resolution calculation. Cc: stable@vger.kernel.org Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: mvebu: cp110: Fix clock tree representationGregory CLEMENT1-55/+39
Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: Re-use DEFINE_SHOW_ATTRIBUTE() macroAndy Shevchenko1-53/+7
...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: bcm2835: Protect sections updating shared registersBoris Brezillon1-0/+4
CM_PLLx and A2W_XOSC_CTRL registers are accessed by different clock handlers and must be accessed with ->regs_lock held. Update the sections where this protection is missing. Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon1-4/+4
ana->maskX values are already '~'-ed in bcm2835_pll_set_rate(). Remove the '~' in the definition to fix ANA setup. Note that this commit fixes a long standing bug preventing one from using an HDMI display if it's plugged after the FW has booted Linux. This is because PLLH is used by the HDMI encoder to generate the pixel clock. Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-18clk: sunxi-ng: add support for the Allwinner H6 CCUIcenowy Zheng4-0/+1269
The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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