| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-05-23 | clk: imx8m: Add GIC clock |   Leonard Crestez | 2 | -0/+8 |
| 2019-05-23 | clk: imx8mm: add SNVS clock to clock tree |   Anson Huang | 1 | -0/+1 |
| 2019-05-22 | clk: imx8mq: add SNVS clock to clock tree | Anson Huang | 1 | -0/+1 |
| 2019-05-21 | clk: ti: clkctrl: Fix clkdm_clk handling |   Tony Lindgren | 1 | -4/+4 |
| 2019-05-21 | clk: imx: imx8mm: fix int pll clk gate |   Peng Fan | 1 | -6/+6 |
| 2019-05-21 | clk: sifive: restrict Kconfig scope for the FU540 PRCI driver |   Paul Walmsley | 1 | -0/+1 |
| 2019-05-21 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 21 |   Thomas Gleixner | 1 | -13/+1 |
| 2019-05-21 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 | Thomas Gleixner | 6 | -78/+6 |
| 2019-05-21 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 4 | Thomas Gleixner | 4 | -8/+4 |
| 2019-05-21 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 | Thomas Gleixner | 6 | -89/+6 |
| 2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 42 | -0/+42 |
| 2019-05-21 | clk: renesas: r8a7796: Add CMM clocks |   Jacopo Mondi | 1 | -0/+3 |
| 2019-05-21 | clk: renesas: r8a779{5|6|65}: Add TPU clock |   Cao Van Dong | 3 | -0/+3 |
| 2019-05-20 | clk: meson: g12a: add controller register init |   Jerome Brunet | 1 | -1/+7 |
| 2019-05-20 | clk: meson: eeclk: add init regs | Jerome Brunet | 2 | -0/+5 |
| 2019-05-20 | clk: meson: g12a: add mpll register init sequences | Jerome Brunet | 1 | -0/+24 |
| 2019-05-20 | clk: meson: mpll: add init callback and regs | Jerome Brunet | 2 | -11/+26 |
| 2019-05-20 | clk: meson: axg: spread spectrum is on mpll2 | Jerome Brunet | 1 | -5/+5 |
| 2019-05-20 | clk: meson: gxbb: no spread spectrum on mpll0 | Jerome Brunet | 1 | -5/+0 |
| 2019-05-20 | clk: meson: mpll: properly handle spread spectrum | Jerome Brunet | 2 | -3/+7 |
| 2019-05-20 | clk: meson: meson8b: fix a typo in the VPU parent names array variable |   Martin Blumenstingl | 1 | -5/+5 |
| 2019-05-20 | clk: meson: fix MPLL 50M binding id typo | Jerome Brunet | 2 | -3/+3 |
| 2019-05-20 | clk: imx8mm: add GPIO clocks to clock tree | Anson Huang | 1 | -0/+5 |
| 2019-05-20 | clk: rockchip: add 1.464GHz cpu-clock rate to rk3228 |   Justin Swartz | 1 | -0/+1 |
| 2019-05-20 | clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase() |   Douglas Anderson | 1 | -3/+3 |
| 2019-05-20 | clk: rockchip: Don't yell about bad mmc phases when getting | Douglas Anderson | 1 | -3/+1 |
| 2019-05-20 | clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation | Douglas Anderson | 1 | -2/+2 |
| 2019-05-16 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux |   Linus Torvalds | 124 | -6/+130 |
| 2019-05-16 | Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc | Linus Torvalds | 1 | -2/+2 |
| 2019-05-15 | clk: Remove io.h from clk-provider.h |   Stephen Boyd | 124 | -6/+130 |
| 2019-05-07 | Merge branch 'clk-parent-rewrite-1' into clk-next | Stephen Boyd | 4 | -113/+322 |
| 2019-05-07 | Merge branch 'clk-ti' into clk-next | Stephen Boyd | 15 | -18/+40 |
| 2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next | Stephen Boyd | 52 | -229/+2265 |
| 2019-05-07 | Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' and 'clk-qoriq' into clk-next | Stephen Boyd | 17 | -66/+576 |
| 2019-05-07 | Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next | Stephen Boyd | 12 | -90/+178 |
| 2019-05-07 | Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next | Stephen Boyd | 29 | -601/+2338 |
| 2019-05-07 | Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next | Stephen Boyd | 52 | -202/+4614 |
| 2019-05-03 | clk: Cache core in clk_fetch_parent_index() without names | Stephen Boyd | 1 | -10/+27 |
| 2019-05-03 | clk: imx: correct pfdv2 gate_bit/vld_bit operations | Anson Huang | 1 | -5/+5 |
| 2019-05-03 | clk: sifive: add a driver for the SiFive FU540 PRCI IP block | Paul Walmsley | 5 | -0/+647 |
| 2019-05-03 | clk: analogbits: add Wide-Range PLL library | Paul Walmsley | 5 | -0/+372 |
| 2019-05-03 | clk: imx: clk-pllv3: mark expected switch fall-throughs |   Gustavo A. R. Silva | 1 | -0/+2 |
| 2019-05-02 | clk: imx8mq: Add dsi_ipg_div |   Guido Günther | 1 | -0/+1 |
| 2019-05-01 | clk: imx: pllv4: add fractional-N pll support | Anson Huang | 1 | -9/+63 |
| 2019-05-01 | clk: sunxi-ng: Use the correct style for SPDX License Identifier |   Nishad Kamdar | 2 | -3/+3 |
| 2019-05-01 | clk: sprd: Use the correct style for SPDX License Identifier | Nishad Kamdar | 6 | -6/+6 |
| 2019-05-01 | clk: renesas: Use the correct style for SPDX License Identifier | Nishad Kamdar | 3 | -6/+6 |
| 2019-05-01 | clk: qcom: Use the correct style for SPDX License Identifier | Nishad Kamdar | 1 | -1/+1 |
| 2019-05-01 | clk: davinci: Use the correct style for SPDX License Identifier | Nishad Kamdar | 2 | -2/+2 |
| 2019-05-01 | clk: actions: Use the correct style for SPDX License Identifier | Nishad Kamdar | 9 | -9/+9 |
