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2017-08-10clk: samsung: exynos542x: Enable clock rate propagation up to the EPLLSylwester Nawrocki1-7/+8
The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL and the audio subsystem clock controller so that the EPLL's output frequency can be set indirectly with clk_set_rate() on a leaf clock. That should be safe as EPLL is normally only used to generate clock for the audio subsystem. With this change we can avoid passing the EPLL clock to the ASoC machine driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-08-09clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocksSylwester Nawrocki1-4/+4
This allows clk rate propagation up to the clock tree so EPLL can be reprogrammed indirectly when setting rate of the Audio Subsystem clocks. The advantage is that sound machine driver can operate only on the leaf clocks rather than explicitly re-configuring the root clock (EPLL). Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-08-09clk: samsung: Fix mau_epll clock definition for exynos5422Sylwester Nawrocki1-3/+9
Parent clock of the MAU_EPLL gate clock on exynos5422 is "mout_user_mau_epll", not "mout_mau_epll_clk". This change only affects exynos5422/5800. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-08-08clk: rockchip: add special approximation to fix up fractional clk's jitterElaine Zhang1-0/+36
>From Rockchips fractional divider description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Therefore add a special approximation function that handles this special requirement. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: fractional-divider: allow overriding of approximationElaine Zhang1-8/+20
Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation. For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies. Therefore add the ability to provide custom approximation functions. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: modify rk3128 clk driver to also support rk3126Elaine Zhang1-14/+55
rk3128 and rk3126 have some gate registers describe differences. So need to make some distinctions. The RK3126 and RK3128 Same clock description we move it to the common clock branches. And the different clks description use the own clock branches. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: add some critical clocks for rv1108 SoCElaine Zhang1-1/+7
the bus/periph/nclk_ddrupctl/pclk_ddrmon/pclk_acodecphy/pclk_pmu no driver to handle them, Chip design requirements for these clock to always on. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: rename some of clks for rv1108 SoCElaine Zhang1-14/+14
Rename some of clks to keep the consistency with the TRM. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: fix up some clks describe error for rv1108 SoCElaine Zhang1-59/+62
1. fix up the parent name 2. remove the CLK_IGNORE_UNUSED flag for some clk not need to always on. 3. fix up some clks regs describe error. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: support more clks for rv1108Elaine Zhang1-2/+276
Add the description of the missing clock, make the clock more complete. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08clk: rockchip: fix up the pll clks error for rv1108 SoCElaine Zhang1-3/+3
fix up the lock_shift describe error. remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-06clk: rockchip: support more rates for rv1108 cpuclkElaine Zhang1-4/+19
fix up the cpuclk rates table for support more freqs. fix up the mux_core_mask describe error. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-04clk: meson: gxbb-aoclk: Add CEC 32k clockNeil Armstrong4-2/+231
The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb-aoclk: Switch to regmap for register accessNeil Armstrong4-23/+95
Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet1-0/+177
Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet1-3/+4
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet1-1/+2
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl3-13/+156
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores). According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione. Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clkidsJerome Brunet1-1/+7
Add the clkids for the clocks feeding the input0 of the mmc controllers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson-gxbb: expose almost every clock in the bindingsJerome Brunet1-110/+7
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson8b: expose every clock in the bindingsJerome Brunet1-99/+4
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed (none on this particular controller at the moment) Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix protection against undefined clksJerome Brunet1-0/+2
gxbb clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: a70c6e06ed7c ("clk: meson: gxbb: protect against holes in the onecell_data array") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: meson8b: fix protection against undefined clksJerome Brunet1-0/+1
meson8b clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: e92f7cca446e ("clk: meson8b: clean up fixed rate clocks") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3Icenowy Zheng1-1/+1
The CPUX clock, which is the main clock of the ARM core on Allwinner H3, can be adjusted by changing the frequency of the PLL_CPUX clock. Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX clock can be adjusted when adjusting the CPUX clock. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-04clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai1-0/+11
This patch utilizes the new PLL clk notifier to gate then ungate the PLL CPU clock after rate changes. This should prevent any system hangs resulting from cpufreq changes to the clk. Reported-by: Ondrej Jirman <megous@megous.com> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-03clk: uniphier: remove sLD3 SoC supportMasahiro Yamada4-45/+20
This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-02Merge branch 'clk-fixes' into clk-nextStephen Boyd7-33/+69
* clk-fixes: clk: keystone: sci-clk: Fix sci_clk_get clk: meson: mpll: fix mpll0 fractional part ignored clk: samsung: exynos5420: The EPLL rate table corrections clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
2017-08-02clk: keystone: sci-clk: Fix sci_clk_getTero Kristo1-24/+42
Currently a bug in the sci_clk_get implementation causes it to always return a clock belonging to the last device in the static list of clock data. This is due to a bug in the init code that causes the array used by sci_clk_get to only be populated with the clocks for the last device, as each device overwrites the entire array with its own clocks. Fix this by calculating the actual number of clocks for the SoC, and allocating the whole array in one go. Also, we don't need the handle to the init data array anymore after doing this, instead we can just compare the dev_id / clk_id against the registered clocks and use binary search for speed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Dave Gerlach <d-gerlach@ti.com> Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Cc: Nishanth Menon <nm@ti.com> Tested-by: Franklin Cooper <fcooper@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-02Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixesStephen Boyd1-1/+1
Pull one Allwinner clock fix from Chen-Yu Tsai: One critical clock fix for sun5i (A10s/A13/R8) which enables propagation of clock rate changes from the "cpu" clock to it's parent PLL clock. This fixes cpufreq related crashes that have been observed on KernelCI with the C.H.I.P. and multi_v7_defconfig. * tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
2017-08-02Merge tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson into clk-fixesStephen Boyd4-0/+18
Pull one Meson clock fix from Neil Armstrong * tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson: clk: meson: mpll: fix mpll0 fractional part ignored
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet4-0/+18
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-01clk: sunxi-ng: Wait for lock when using fractional modeJernej Škrabec4-4/+8
Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be set before returning. Because of that, unstable clock may be used. Add a wait for lock in the helper function. Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01clk: sunxi-ng: Make fractional helper less chattyJernej Škrabec1-5/+5
ccu_frac_helper_read_rate() prints some info which is not really helpful except during debugging. Replace printk() with pr_debug(). Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01clk: sunxi-ng: multiplier: Fix fractional modeJernej Škrabec1-2/+5
Driver for multiplier clock is missing a call to ccu_frac_helper_enable() when fractional mode is selected. Add a call to ccu_frac_helper_enable(). Fixes: d77e8135b340 ("clk: sunxi-ng: multiplier: Add fractional support") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01clk: sunxi-ng: Fix fractional mode for N-M clocksJernej Škrabec1-2/+14
N-M factor clock driver is missing a call to ccu_frac_helper_enable() when fractional mode is used. Additionally, most SoCs require that M factor must be set to 0 when fractional mode is used. Without this patch, clock keeps the old value and clk_set_rate() returns without error. Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support") CC: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-07-31clk: samsung: exynos5420: The EPLL rate table correctionsSylwester Nawrocki1-8/+8
This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-27clk: sunxi-ng: Fix header guard of ccu-sun8i-r.hMatthias Kaehlcke1-1/+1
Remove trailing extra underscore in definition of _CCU_SUN8I_R_H Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-07-24clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard1-1/+1
The current CPU clock is missing the option to change the rate of its parents, leading to improper rates calculated by cpufreq, and eventually crashes. Cc: <stable@vger.kernel.org> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Reported-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring25-80/+61
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21clk: qoriq: add pll clock to clock lookup tableYuantian Tang1-0/+7
Register each PLL and its division clocks to clock lookup table to facilitate the clock look up for clock consumer. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21clk: qoriq: add clock configuration for ls1088a socYuantian Tang1-0/+12
Clock on ls1088a chip takes primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-19clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang1-26/+20
Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-19clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang1-2/+1
'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-18Merge branch 'clk-fixes' into clk-nextStephen Boyd2-0/+21
* clk-fixes: clk: x86: Do not gate clocks enabled by the firmware clk: gemini: Fix reset regression
2017-07-18clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione1-0/+7
Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Darren Hart (VMware) <dvhart@infradead.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mmp: Drop unnecessary staticJulia Lawall1-1/+1
Drop static on a local variable, when the variable is initialized before any possible use. Thus, the static has no benefit. The semantic patch that fixes this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: moxart: remove unnecessary staticsGustavo A. R. Silva1-2/+2
Remove unnecessary static on local variable _base_ in both functions moxart_of_pll_clk_init() and moxart_of_apb_clk_init(). Such variables are initialized before being used, on every execution path throughout the mentioned functions. The statics have no benefit and, removing them reduce the code size. This issue was detected using Coccinelle and the following semantic patch: @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; In the following log you can see the difference in the code size. Also, notice that the bss segment is reduced down to zero. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 1724 384 128 2236 8bc drivers/clk/clk-moxart.o after: text data bss dec hex filename 1697 240 0 1937 791 drivers/clk/clk-moxart.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: qcom: clk-smd-rpm: Fix the reported rate of branchesGeorgi Djakov1-2/+0
As there is no way to actually query the hardware for the current clock rate, now racalc_rate() just returns the last rate that was previously set. But if the rate was not set yet, we return the bogus rate of 1000Hz. The branch clocks have the same rate as their parent, so in this case we just need to remove recalc_rate ops and then the core framework will handle this automagically. The round_rate() is unused, so remove it as well. Reported-by: Archit Taneja <architt@codeaurora.org> Fixes: 00f64b58874e ("clk: qcom: Add support for SMD-RPM Clocks") Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mediatek: fixed static checker warning in clk_cpumux_get_parent callSean Wang1-4/+0
Fixed the signedness bug returning '(-22)' on the return type as u8 with removing the sanity checker in clk_cpumux_get_parent() since clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent() got called. Fixes: 1e17de9049da ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: gemini: Fix reset regressionLinus Walleij1-0/+14
commit e2860e1f62f2 ("serial: 8250_of: Add reset support") introduced reset support for the 8250_of driver. However it unconditionally uses the assert/deassert pair to deassert reset on the device at probe and assert it at remove. This does not work with systems that have a self-deasserting reset controller, such as Gemini, that recently added a reset controller. As a result, the console will not probe on the Gemini with this message: Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled of_serial: probe of 42000000.serial failed with error -524 This (-ENOTSUPP) is the error code returned by the deassert() operation on self-deasserting reset controllers. To work around this, implement dummy .assert() and .deassert() operations in the Gemini combined clock and reset controller. This fixes the issue on this system. Cc: Joel Stanley <joel@jms.id.au> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-serial@vger.kernel.org Fixes: e2860e1f62f2 ("serial: 8250_of: Add reset support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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