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path: root/drivers/cxl/cxl.h (follow)
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2022-08-05cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya1-0/+2
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams1-0/+2
2022-08-01cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter1-1/+1
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams1-1/+35
2022-07-26cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams1-0/+1
2022-07-26cxl/region: Add region driver boiler plateDan Williams1-0/+1
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-1/+12
2022-07-25cxl/region: Program target listsDan Williams1-0/+2
2022-07-25cxl/region: Attach endpoint decodersDan Williams1-0/+20
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams1-0/+2
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams1-0/+11
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams1-0/+2
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky1-0/+33
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky1-0/+25
2022-07-21cxl/region: Add region creation supportBen Widawsky1-0/+18
2022-07-21cxl/mem: Enumerate port targets before adding endpointsDan Williams1-0/+5
2022-07-21cxl/port: Move dport tracking to an xarrayDan Williams1-5/+7
2022-07-21cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams1-3/+1
2022-07-21cxl/port: Record parent dport when adding portsDan Williams1-2/+5
2022-07-21cxl/port: Record dport in endpoint referencesDan Williams1-0/+2
2022-07-21cxl/hdm: Track next decoder to allocateDan Williams1-0/+2
2022-07-21cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams1-0/+9
2022-07-21cxl/hdm: Enumerate allocated DPADan Williams1-0/+2
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams1-1/+14
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams1-2/+13
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-8/+22
2022-07-19cxl/port: Read CDAT tableIra Weiny1-0/+7
2022-07-11cxl/pmem: Delete unused nvdimm attributeDan Williams1-1/+0
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams1-0/+2
2022-07-09cxl: Introduce cxl_to_{ways,granularity}Dan Williams1-0/+26
2022-07-09cxl/core: Drop is_cxl_decoder()Dan Williams1-1/+0
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams1-5/+1
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams1-2/+2
2022-06-21cxl/core: Use is_endpoint_decoderBen Widawsky1-0/+1
2022-04-28cxl: Drop cxl_device_lock()Dan Williams1-78/+0
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky1-0/+1
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky1-0/+6
2022-02-08cxl/core/port: Add switch port enumerationDan Williams1-0/+19
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-4/+4
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-0/+4
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams1-6/+27
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams1-12/+4
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams1-0/+1
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams1-0/+3
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams1-0/+2
2022-02-08cxl: Prove CXL lockingDan Williams1-0/+81
2022-02-08cxl/core: Track port depthBen Widawsky1-0/+2
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky1-1/+15
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky1-2/+6
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky1-0/+3