aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/cxl (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-09-09Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds13-723/+988
2021-09-07cxl/registers: Fix Documentation warningDan Williams1-1/+14
2021-09-07cxl/pmem: Fix Documentation warningDan Williams1-2/+28
2021-09-07cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)1-2/+2
2021-09-07cxl/pci: Fix lockdown levelDan Williams1-1/+1
2021-09-07cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge portsAlison Schofield1-4/+8
2021-08-10cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny1-8/+6
2021-08-10cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny2-5/+96
2021-08-07cxl/pci: Store memory capacity valuesIra Weiny2-3/+37
2021-08-06cxl/pci: Simplify register setupBen Widawsky3-27/+13
2021-08-06cxl/pci: Ignore unknown register block typesBen Widawsky1-8/+12
2021-08-06cxl/core: Move memdev management to coreBen Widawsky6-234/+275
2021-08-06cxl/pci: Introduce cdevm_file_operationsDan Williams2-27/+53
2021-08-06cxl/core: Move register mapping infrastructureDan Williams3-228/+237
2021-08-06cxl/core: Move pmem functionalityDan Williams4-202/+225
2021-08-06cxl/core: Improve CXL core kernel docsBen Widawsky1-2/+9
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky6-7/+10
2021-07-21bus: Make remove callback return voidUwe Kleine-König1-2/+1
2021-06-17cxl/pci: Rename CXL REGLOC IDBen Widawsky2-2/+2
2021-06-17cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield1-0/+122
2021-06-17cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield1-5/+95
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams5-16/+215
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams6-2/+335
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams2-0/+95
2021-06-14cxl/pci: Add media provisioning required commandsBen Widawsky1-0/+19
2021-06-12cxl/component_regs: Fix offsetBen Widawsky1-1/+1
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky2-1/+8
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams3-1/+347
2021-06-09cxl/acpi: Enumerate host bridge root portsDan Williams1-1/+92
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams3-4/+167
2021-06-09cxl/Kconfig: Default drivers to CONFIG_CXL_BUSDan Williams1-0/+2
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams5-0/+247
2021-06-05cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams1-7/+8
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky3-6/+166
2021-06-05cxl/pci: Reserve individual register block regionsIra Weiny2-4/+34
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny3-38/+180
2021-06-05cxl/pci: Reserve all device regions at onceIra Weiny1-7/+11
2021-06-05cxl/pci: Introduce cxl_decode_register_block()Ira Weiny1-8/+18
2021-05-26cxl/mem: Get rid of @cxlm.baseBen Widawsky2-15/+11
2021-05-26cxl/mem: Move register locator logic into reg setupBen Widawsky1-67/+68
2021-05-26cxl/mem: Split creation from mapping in probeBen Widawsky1-24/+40
2021-05-26cxl/mem: Use dev instead of pdev->devBen Widawsky1-1/+1
2021-05-26cxl/mem: Demarcate vendor specific capability IDsBen Widawsky1-1/+4
2021-05-26cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma2-0/+15
2021-05-26cxl: Rename mem to pciBen Widawsky3-16/+10
2021-05-14cxl/core: Refactor CXL register lookup for bridge reuseDan Williams3-44/+66
2021-05-14cxl/core: Rename bus.c to core.cDan Williams2-9/+10
2021-05-14cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams3-28/+61
2021-05-14cxl/mem: Move some definitions to mem.hDan Williams3-77/+82
2021-04-16cxl/mem: Fix memory device capacity probingDan Williams1-2/+5
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.