aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32
AgeCommit message (Expand)AuthorFilesLines
2022-11-02drm/amd/display: Set memclk levels to be at least 1 for dcn32Dillon Varone1-0/+3
2022-11-02drm/amd/display: Limit dcn32 to 1950Mhz display clockJun Lei1-4/+4
2022-10-10drm/amd/display: Fix bug preventing FCLK Pstate allow message being sentDillon Varone1-2/+2
2022-10-10drm/amd/display: Acquire FCLK DPM levels on DCN32Dillon Varone1-14/+27
2022-10-06drm/amd/display: Reorder FCLK P-state switch sequence for DCN32Dillon Varone1-21/+23
2022-09-29drm/amd/display: fill in clock values when DPM is not enabledSamson Tam1-0/+14
2022-07-25drm/amd/display: Drop FPU flags from dcn32_clk_mgrRodrigo Siqueira1-77/+4
2022-07-05drm/amd/display: Switch to correct DTO on HDMIChris Park1-0/+2
2022-07-05drm/amd/display: Add SubVP required codeAlvin Lee1-2/+3
2022-06-30drm/amdgpu/display: add missing FP_START/END checks dcn32_clk_mgr.cAlex Deucher1-0/+4
2022-06-30drm/amd/display: Fix __nedf2 undefined for 32 bit compilationRodrigo Siqueira1-4/+7
2022-06-30drm/amd/display: Fix __muldf3 undefined for 32 bit compilationRodrigo Siqueira1-2/+2
2022-06-23drm/amd/display: Fix indentation in dcn32_get_vco_frequency_from_reg()Nathan Chancellor1-1/+1
2022-06-21drm/amd/display: Drop duplicate defineRodrigo Siqueira1-2/+0
2022-06-21drm/amd/display: Update hook dcn32_funcsRodrigo Siqueira1-1/+2
2022-06-21drm/amd/display: Implement a pme workaround functionChaitanya Dhere3-1/+10
2022-06-21drm/amd/display: Get VCO frequency from registersRodrigo Siqueira1-1/+93
2022-06-21drm/amd/display: Update SW state correctly for FCLKAlvin Lee1-3/+3
2022-06-21drm/amd/display: Fix divide-by-zero in DPPCLK and DISPCLK calculationGeorge Shen1-8/+10
2022-06-21drm/amd/display: Update DPPCLK programming sequenceAlvin Lee1-1/+24
2022-06-21drm/amd/display: Check minimum disp_clk and dpp_clk debug optionRodrigo Siqueira1-0/+19
2022-06-06drm/amdgpu/display: make some functions staticAlex Deucher1-1/+1
2022-06-03drm/amd/display: Implement DTBCLK ref switching on dcn32Alvin Lee3-15/+91
2022-06-03drm/amd/display: Match dprefclk with clk registersSamson Tam1-3/+6
2022-06-03drm/amd/display: cleaning up smu_if to add future flexibilityMartin Leung3-15/+74
2022-06-03drm/amd/display: FCLK P-state support updatesChaitanya Dhere2-5/+7
2022-06-03drm/amd/display: Introduce new update_clocks logicJun Lei1-52/+73
2022-06-03drm/amd/display: Disable DTB Ref Clock Switching in dcn32Dillon Varone1-0/+4
2022-06-03drm/amd/display: Halve DTB Clock Value for DCN32Fangzhi Zuo1-1/+1
2022-06-03drm/amd/display: Add additional guard for FCLK pstate message for DCN321Dillon Varone1-3/+4
2022-06-03drm/amd/display: Implement WM table transfer for DCN32/DCN321Alvin Lee1-0/+7
2022-06-03drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321Dillon Varone1-1/+2
2022-06-03drm/amd/display: add CLKMGR changes for DCN32/321Aurabindo Pillai6-0/+1006
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.