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path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-09-19drm/amd/display: update dccg based on HW deltaCharlene Liu1-0/+1
2022-06-03drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai1-1/+33
2022-01-25drm/amd/display: Disable physym clockDavid Galiffi1-2/+6
2022-01-25drm/amd/display: Fix disabling dccg clocksDavid Galiffi1-0/+7
2021-10-19drm/amd/display: Disable hdmistream and hdmichar clocksJake Wang1-2/+7
2021-10-19drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_leJake Wang1-1/+14
2021-10-19drm/amd/display: Disable dsc root clock when not being usedJake Wang1-1/+15
2021-06-22drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher1-8/+0
2021-06-08drm/amd/display: Add interface for ADD & DROP PIXEL RegistersWesley Chalmers1-5/+47
2021-06-08drm/amd/display: Add Interface to set FIFO ERRDET SW OverrideWesley Chalmers1-3/+26
2021-06-04drm/amd/display: Add DCN3.1 DCCGNicholas Kazlauskas1-0/+54
2020-11-04drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher1-8/+0
2020-07-01drm/amd/display: Add DCN3 DCCGBhawanpreet Lakha1-0/+22
2019-10-03drm/amd/display: Revert fixup DPP programming sequenceWesley Chalmers1-1/+1
2019-08-15drm/amd/display: fixup DPP programming sequenceJun Lei1-1/+1
2019-06-21drm/amd/display: Add DCN2 clk mgrHarry Wentland1-0/+116