aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/display/dc/dcn314 (follow)
AgeCommit message (Collapse)AuthorFilesLines
2022-11-09drm/amd/display: Fix reg timeout in enc314_enable_fifoNicholas Kazlauskas1-6/+18
[Why] The link enablement sequence can end up resetting the encoder while the PHY symclk isn't yet on. This means that waiting for symclk on will timeout, along with the reset bit never asserting high. This causes unnecessary delay when enabling the link and produces a warning affecting multiple IGT tests. [How] Don't wait for the symclk to be on here because firmware already does. Don't wait for reset if we know the symclk isn't on. Split the reset into a helper function that checks the bit and decides whether or not a delay is sufficient. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x
2022-11-02drm/amd/display: Update DSC capabilitie for DCN314Leo Chen1-1/+1
dcn314 has 4 DSC - conflicted hardware document updated and confirmed. Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x
2022-10-10drm/amd/display: Update PMFW z-state interface for DCN314Nicholas Kazlauskas1-1/+2
[Why] Request from PMFW to change the messaging format to specify whether we support z-state via individual bits. [How] Update the args we pass in the support message. Fixes: d5c6909e7460 ("drm/amd/display: Add DCN314 clock manager") Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0
2022-10-06drm/amd/display: Refactor edp ILR caps codesIan Chen1-1/+12
We split out ILR config from "global" to "per-panel" config settings. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-06drm/amd/display: change to enc314_stream_encoder_dp_blank staticYang Yingliang1-1/+1
enc314_stream_encoder_dp_blank is only used in dcn314_dio_stream_encoder.c now, change it to static. Fixes: c55bf690fe79 ("drm/amd/display: Add explicit FIFO disable for DP blank") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-29drm/amd/display: Fix typo in get_pixel_rate_divTaimur Hassan1-1/+1
[Why & How] Some FIFO errors still occur due to reading wrong pixel rate divider. Fix typo to prevent FIFO error. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-29drm/amd/display: Add explicit FIFO disable for DP blankNicholas Kazlauskas1-1/+11
[Why] We rely on DMCUB to do this when disabling the link but it should actually come before we disable the DP VID stream. If we don't then the FIFO can end up with underflow that persists the next time it's enabled. [How] Add a DCN314 specific blank sequence that will disable the DIG FIFO first. Reviewed-by: Syed Hassan <Syed.Hassan@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-29drm/amd/display: Do DIO FIFO enable after DP video stream enableNicholas Kazlauskas1-5/+8
[Why] Avoids a race condition where DIO FIFO can underflow due to no incoming data available. [How] Shift the FIFO enable below stream enable. Make sure fullness level is written before the DIO reset takes place and that we're not doing it twice. Reviewed-by: Syed Hassan <Syed.Hassan@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-29drm/amd/display: Avoid avoid unnecessary pixel rate divider programmingTaimur Hassan1-0/+47
[Why] Programming pixel rate divider when FIFO is enabled can cause FIFO error. [How] Skip divider programming when divider values are the same to prevent FIFO error. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: correct num_dsc based on HW capCharlene Liu1-1/+1
[why] num_dsc is 3 for dcn314 based on HW capablity. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: update dccg based on HW deltaCharlene Liu1-18/+52
[why] update hw dccg based on HW delta, and reuse common src code Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: Add shift and mask for ICH_RESET_AT_END_OF_LINEDaniel Miess1-3/+6
[Why] DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE shift and mask being missing [How] Add in shift and mask for ICH_RESET_AT_END_OF_LINE Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Daniel Miess <Daniel.Miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: Ignore k1/k2 values for virtual signalRodrigo Siqueira1-0/+3
[Why and How] We are hitting k1/k2 assert when we are using a virtual signal in the test; as a result, we are failing some automated tests with a false positive. This commit addresses this issue by ignoring the assert condition if we use SIGNAL_TYPE_VIRTUAL. Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: rework recent update PHY state commitWenjing Liu1-0/+4
[why] Original change 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: Only consider pixle rate div policy for DCN32+Alvin Lee3-17/+2
[Why and How] - Only consider pixel rate div policy for DCN32+ Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-14drm/amd/display: make some functions staticJiapeng Chong1-3/+3
These functions are not used outside the file dcn32_hubbub.c, so the modification is defined as static. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:223:6: warning: no previous prototype for ‘dccg314_set_valid_pixel_rate’. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:184:6: warning: no previous prototype for ‘dccg314_set_dpstreamclk’. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:140:6: warning: no previous prototype for ‘dccg314_set_dtbclk_dto’. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2144 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-14drm/amd/display: make optc314_phantom_crtc_post_enable staticJiapeng Chong1-1/+1
This symbol is not used outside of dcn314_optc.c, so marks it static. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:153:6: warning: no previous prototype for ‘optc314_phantom_crtc_post_enable’. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2147 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-14drm/amd/display: make enc314_stream_encoder_dvi_set_stream_attribute staticJiapeng Chong1-1/+1
This symbol is not used outside of dcn314_dio_stream_encoder.c, so marks it static. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dio_stream_encoder.c:84:6: warning: no previous prototype for ‘enc314_stream_encoder_dvi_set_stream_attribute’. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2146 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-13drm/amd/display: Fixing DIG FIFO ErrorLeo Chen1-2/+1
[Why & How] DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software. Removed all instances of resetting the register to 0 Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: fix wrong register accessCharlene Liu1-0/+1
[why] fw version check was for release branch. for staging, it has a chance to enter wrong code path. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Missing HPO instance addedLeo Chen1-0/+1
[Why & How] Number of encoder is set to 4 but only 3 instances are created. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Cleanup PSR flagGabe Teeger1-1/+0
[Why] enable_sw_cntl_psr flag is not needed. For PSR1 and PSR2, we should be passing dirty rectangle and cursor updates to FW regardless of enable_sw_cntl_psr flag. [How] Remove enable_sw_cntl_psr flag from driver. Send cursor info and dirty rectagle status to dmub only in the case of dcn31 and above. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix OTG H timing reset for dcn314Duncan Ma1-1/+2
[Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: remove possible condition with no effect (if == else)Bernard Zhao1-2/+0
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c:1816:6-8: WARNING: possible condition with no effect (if == else). Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: fix potential memory leakBernard Zhao1-0/+1
This patch fix potential memory leak (clk_src) when function run into last return NULL. Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: fix potential memory leakBernard Zhao1-0/+1
This patch fix potential memory leak (clk_src) when function run into last return NULL. s/free/kfree/ - Alex Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-22drm/amd/display: enable PCON support for dcn314Roman Li1-0/+1
[Why] DCN314 supports PCON. [How] Explicitly enable it in dcn314 resources. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-10drm/amd/display: Fix VPG instancing for dcn314 HPODuncan Ma1-2/+3
[Why] An issue during VPG indexing offset generation causing to use the incorrect VPG. HW team placed VPG instances 5 at end of list, making it VPG 9 in register headers. [How] Correct VPG instance for HPO encoders. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-10drm/amd/display: Fix TMDS 4K@60Hz YCbCr420 corruption issueDaniel Miess3-0/+34
[Why] DIG_FIFO_OUTPUT_PIXEL_MODE not being set for dcn314 resulting in incorrect timing for YCbCr4:2:0 [How] Copy the implementation of set_pixels_per_cycle from dcn32 over to dcn314 Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Daniel Miess <Daniel.Miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-10drm/amd/display: Drop FPU flags from MakefileRodrigo Siqueira1-25/+0
At this point, we isolate the FPU code associated with DCN314 under the DML folder. This commit drops the FPU flags from the Makefile. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-10drm/amd/display: Move populate dml pipes from DCN314 to dmlRodrigo Siqueira1-97/+4
The function responsible for populating DML pipes has some FPU operations, and for this reason, it must be moved to the dml folder. This commit moves such function from resource to the fpu file under the dml folder. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-10drm/amd/display: Create FPU files for DCN314Rodrigo Siqueira2-231/+7
DCN314 has multiple references to FPU operations inside the resource files, and we need to move those codes to the DML folder. This commit creates the dcn314_fpu files and moves the bounding box operation to this file. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-10drm/amd/display: Use pixels per container logic for DCN314 DCCG dividersDaniel Miess1-7/+7
[Why] DP DSC YCbCr422 not working because dcn314_calculate_dccg_k1_k2_values does not account for two pixels per container [How] Replace the contents of dcn314_calculate_dccg_k1_k2_values with the code from the function dcn32_calculate_dccg_k1_k2_values Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Daniel Miess <Daniel.Miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Add dc_ctx to link_enc_create() parametersAurabindo Pillai1-0/+1
[Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is needed to get the dc_ctx handle where register offset initialization routine is called. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Fix dpstreamclk programmingMichael Strauss1-6/+7
[WHY] Currently programming incorrect hpo inst as well as selecting incorrect source [HOW] Use hpo inst instead of otg inst to select dpstreamclk inst Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Add missing AUDIO_DTO_SEL reg fieldMichael Strauss1-1/+2
[WHY] Needed to program audio dto Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Add OTG/ODM functionsMichael Strauss1-0/+34
[WHY] Required for correct OTG_H_TIMING_CNTL programming Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Use correct clock source constructor for DCN314Michael Strauss1-1/+1
[WHY] Previously was pointing to DCN3 clock constructor rather than DCN31's Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Add pixel rate div calcs and programmingMichael Strauss4-0/+56
[WHY/HOW] Need to calculate and set some pixel rate divisors on correct otg_inst Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Guard against zero memory channelsNicholas Kazlauskas1-1/+4
[Why] If BIOS doesn't specify number of memory channels then bandwidth validation will fail due to insufficient BW in DML. [How] If BIOS is setting zero channels then use the default in the table. If no entry is in the table and no BIOS value is specified then throw an ASSERT for future developers to look into. Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Fix OPTC function pointers for DCN314Nicholas Kazlauskas1-1/+2
[Why] Access violation occurs when swapping between HDMI and FRL monitors because we're missing the immediate_disable_crtc callback and it's required for the DCN314 clk manager. [How] Update the table to match the DCN31 optc functions for ones that should be the same: - immediate_disable_crtc - configure_crc Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: Add enable/disable FIFO callbacks to stream setupNicholas Kazlauskas1-12/+26
[Why] We don't write out attributes after disabling and re-enabling the link on some monitors, causing some, but not all, HDMI displays to fail to lightup on DCN314. [How] Firmware used to do this after DIG link setup. Since firmware is no longer doing this to support USB4 and dynamic link remapping we'll need to add this to driver in the equivalent paths. New optional callbacks were created in the stream encoder interface and implementations were added for DCN314. Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-25drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folderMelissa Wen1-0/+1
Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in dcn31_resource that is not FPU protected. Move this function to dcn31_fpu file as part of the work to isolate FPU code. Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: remove duplicate dcn314 includesAlex Deucher3-3/+0
Several headers were included twice. Fix that. Reported-by: kernel test robot <yujie.liu@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN314 DC resourcesRoman Li13-0/+4693
Display Core support for DCN 3.1.4 v2:(squash)fix non-x86 in dc/dcn314/Makefile Properly handle PPC as well. (Alex) v3: minor cleanup (Alex) v4: fix comment (Alex) Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.