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path: root/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-03-19drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headersTom St Denis1-0/+2
2018-10-12drm/amdgpu/vcn:Add new register offset/mask for VCNJames Zhu1-0/+14
2018-09-26drm/amdgpu:Add new register offset/mask to support VCN DPG modeJames Zhu1-0/+8
2018-08-27drm/amdgpu: add system interrupt register offset headerBoyuan Zhang1-0/+2
2018-06-15drm/amdgpu: add more jpeg register offset headersBoyuan Zhang1-0/+20
2017-12-06drm/amd/include:cleanup raven1 vcn header files.Feifei Xu1-0/+376