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path: root/drivers/gpu/drm/amd/include/asic_reg (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-03-29drm/amdgpu: add the VCE 4.0 register headersAlex Deucher3-0/+818
2017-03-29drm/amdgpu: add the UVD 7.0 register headersAlex Deucher3-0/+1160
2017-03-29drm/amdgpu: add THM 9.0 register headersAlex Deucher3-0/+1871
2017-03-29drm/amdgpu: add SMUIO 9.0 register headersAlex Deucher3-0/+533
2017-03-29drm/amdgpu: add SDMA 4.0 register headersAlex Deucher6-0/+5316
2017-03-29drm/amdgpu: add OSSSYS 4.0 register headersAlex Deucher3-0/+1699
2017-03-29drm/amdgpu: add NBIO 6.1 register headersAlex Deucher3-0/+159873
2017-03-29drm/amdgpu: add NBIF 6.1 register headersAlex Deucher3-0/+13240
2017-03-29drm/amdgpu: add MP 9.0 register headersAlex Deucher3-0/+2180
2017-03-29drm/amdgpu: add the MMHUB 1.0 register headersAlex Deucher3-0/+13105
2017-03-29drm/amdgpu: add the HDP 4.0 register headersAlex Deucher3-0/+927
2017-03-29drm/amdgpu: add the GC 9.0 register headersAlex Deucher3-0/+40971
2017-03-29drm/amdgpu: Add the DCE 12.0 register headersAlex Deucher3-0/+92697
2017-03-29drm/amdgpu: Add ATHUB 1.0 register headersAlex Deucher3-0/+2739
2017-03-29drm/amdgpu: add vega10_enum.hAlex Deucher1-0/+22531
2017-03-29drm/amdgpu: add soc15ip.hAlex Deucher1-0/+1343
2017-03-29drm/amd/powerplay: add a new register define for APU in VI.Rex Zhu2-0/+3
2017-03-29drm/amdgpu: implement PRT for GFX6 v2Christian König1-0/+4
2017-02-13drm/amdgpu: read hw register to check pg status.Rex Zhu7-1/+12
2017-02-08drm/amdgpu: add current_pg_status register define for smu7.1Rex Zhu1-0/+1
2017-01-27drm/amdgpu: move misc si headers into amdgpuAlex Deucher2-3402/+0
2017-01-27drm/amdgpu: remove unused header si_reg.hAlex Deucher1-105/+0
2017-01-27drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register definesHarry Wentland8-0/+50
2017-01-27drm/amd/amdgpu: Add HDMI_DATA_SCRAMBLE register definitionHarry Wentland2-0/+4
2016-12-13Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds19-0/+54132
2016-12-12treewide: Make remaining source files non-executableJoe Perches2-0/+0
2016-11-23drm/amd/amdgpu: port of DCE v6 to new headers (v3)Tom St Denis1-0/+12
2016-11-11drm/amd/amdgpu: add SI defines/registersTom St Denis2-0/+27
2016-11-11drm/amd/amdgpu: Introduction of SI registers (v2)Tom St Denis16-0/+54087
2016-10-25drm/amdgpu:use smc_index_11 for VIMonk Liu3-0/+6
2016-09-19drm/amdgpu: implement raster configuration for gfx v6Huang Rui1-0/+35
2016-08-31drm/amdgpu: add si implementation v10Ken Wang1-0/+45
2016-08-31drm/amdgpu: add DMA implementation for si v8Ken Wang1-0/+2
2016-08-31drm/amdgpu: add display controller implementation for si v10Ken Wang1-33/+4
2016-08-31drm/amdgpu: add si header files v4Ken Wang3-0/+3454
2016-08-24drm/amdgpu: switch UVD code to use UVD_NO_OP for paddingAlex Deucher2-0/+2
2016-08-24drm/amdgpu: add support for UVD_NO_OP registerAlex Deucher1-0/+1
2016-07-29drm/amdgpu: add new definition in bif headerHuang Rui1-0/+1
2016-07-29drm/amdgpu: implement UVD VM mode for Stoney v2Christian König1-0/+2
2016-07-07drm/amd/powerplay: add shared definitions for di/dt feature.Rex Zhu2-0/+83
2016-07-07drm/amdgpu: remove gfx8 registers that vary between asicsKen Wang1-22/+0
2016-07-07drm/amdgpu/gfx80: Add QUICK_PG bit to GFX header and use it.Tom St Denis1-2/+4
2016-05-04drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3DFlora Cui1-0/+2
2016-05-04drm/amd: add DCE 11.2 register headersAlex Deucher3-0/+35575
2016-05-04drm/amdgpu: handle more than 10 UVD sessions (v2)Arindam Nath1-0/+1
2016-03-17drm/amdgpu/gfx7: add MTYPE definitionFlora Cui1-0/+6
2016-02-12drm/amd/include: Update dce 8 headers for dalHarry Wentland2-0/+13
2016-02-10drm/amd: add dce8 enum register headerAlex Deucher1-0/+1117
2015-12-21drm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.hyanyang11-0/+1
2015-12-02drm/amd: add new gfx8 register definitions for EDCAlex Deucher1-0/+13
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