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path: root/drivers/gpu/drm/amd
AgeCommit message (Expand)AuthorFilesLines
2022-06-06drm/amd/display: Set PSR level to enable ALPM by defaultDavid Zhang2-1/+7
2022-06-06drm/amd/display: fix system hang when PSR exitsDavid Zhang2-0/+23
2022-06-06drm/amd/display: add vline time in micro sec to PSR contextDavid Zhang3-0/+5
2022-06-06drm/amd/display: Set default value of line_capture_indicationDavid Zhang1-0/+1
2022-06-06drm/amd/display: Passing Y-granularity to dmub fwDavid Zhang3-0/+18
2022-06-06drm/amd/amdgpu: add pipe1 hardware supportArunpravin Paneer Selvam1-1/+1
2022-06-06drm/amd/amdgpu: Enable high priority gfx queueArunpravin Paneer Selvam5-27/+81
2022-06-06drm/amdgpu: adding device coredump supportSomalapuram Amaranath2-0/+69
2022-06-06drm/amdgpu: save the reset dump register value for devcoredumpSomalapuram Amaranath3-3/+11
2022-06-06drm/amd/display: program PSR2 DPCD ConfigurationDavid Zhang2-2/+34
2022-06-06drm/amd/display: revise Start/End SDP dataDavid Zhang1-2/+27
2022-06-06drm/amd/display: update GSP1 generic info packet for PSRSUDavid Zhang1-0/+15
2022-06-06drm/amd/display: combine dirty rectangles in DMUB FWDavid Zhang2-0/+59
2022-06-06drm/amd/display: feed PSR-SU as psr version to dmub FWDavid Zhang1-0/+3
2022-06-04Merge tag 'bitmap-for-5.19-rc1' of https://github.com/norov/linuxLinus Torvalds2-2/+2
2022-06-03drm/amd/display: align dmub cmd header to latest dmub FW to support PSR-SUDavid Zhang1-5/+245
2022-06-03drm/amdgpu/display/dc: Add ACP_DATA registerAlan Liu2-0/+3
2022-06-03drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCNAlex Deucher1-0/+4
2022-06-03drm/amd/display: Add ODM seamless boot supportDuncan Ma5-3/+38
2022-06-03drm/amd/display: Implement DTBCLK ref switching on dcn32Alvin Lee10-31/+118
2022-06-03drm/amd/display: Match dprefclk with clk registersSamson Tam1-3/+6
2022-06-03drm/amd/display: cleaning up smu_if to add future flexibilityMartin Leung4-16/+78
2022-06-03drm/amd/display: update disp pattern generator routine for DCN30Aurabindo Pillai1-31/+2
2022-06-03drm/amd/display: Updates for OTG and DCCG clocksSamson Tam3-1/+9
2022-06-03drm/amd/display: FCLK P-state support updatesChaitanya Dhere2-5/+7
2022-06-03drm/amd/display: Introduce new update_clocks logicJun Lei1-52/+73
2022-06-03drm/amd/display: set link fec status during init for DCN32Jingwen Zhu1-1/+5
2022-06-03drm/amd/display: add new pixel rate programmingJun Lei10-8/+95
2022-06-03drm/amd/display: Remove W/A for ODM memory pinsAlvin Lee2-2/+2
2022-06-03drm/amdgpu: fix up comment in amdgpu_device_asic_has_dc_support()Alex Deucher1-1/+1
2022-06-03drm/amd/display: do not override CURSOR_REQ_MODE when SubVP is not enabledSamson Tam1-2/+5
2022-06-03drm/amdgpu: delete duplicate condition in gfx_v11_0_soft_reset()Dan Carpenter1-11/+9
2022-06-03drm/amdgpu/swsmu: use new register offsets for smu_cmn.cAlex Deucher1-70/+7
2022-06-03drm/amd/display: change dsc image width cap for dcn32 and dcn321Dillon Varone2-0/+6
2022-06-03drm/amdgpu/swsmu: add SMU mailbox registers in SMU contextAlex Deucher17-0/+86
2022-06-03drm/amd/display: Disable DTB Ref Clock Switching in dcn32Dillon Varone1-0/+4
2022-06-03drm/amdgpu/gmc11: enable AGP apertureAlex Deucher4-9/+11
2022-06-03drm/amdgpu: convert nbio_v2_3_clear_doorbell_interrupt() to IP versionAlex Deucher1-1/+1
2022-06-03drm/amd/display: set dram speed for all statesDillon Varone2-2/+10
2022-06-03drm/amdgpu: simplify the logic in amdgpu_device_parse_gpu_info_fw()Alex Deucher1-29/+0
2022-06-03drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP versionAlex Deucher1-5/+5
2022-06-03drm/amd/display: Halve DTB Clock Value for DCN32Fangzhi Zuo1-1/+1
2022-06-03drm/amd/display: Add additional guard for FCLK pstate message for DCN321Dillon Varone1-3/+4
2022-06-03drm/amdgpu: fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7Xiaojian Du1-1/+7
2022-06-03drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0Xiaojian Du2-0/+14
2022-06-03drm/amdgpu: add apu sequence in the imu v11Huang Rui2-4/+9
2022-06-03drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu functionHuang Rui7-1/+44
2022-06-03drm/amdgpu/pm: update MP v13_0_4 smu message register marcoHuang Rui1-0/+20
2022-06-03drm/amdgpu: add mmhub v3_0_1 ip blockHuang Rui4-1/+589
2022-06-03drm/amdgpu: add mmhub v3_0_1 headersHuang Rui2-0/+9252
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