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path: root/drivers/gpu/drm/i915/display/icl_dsi.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-10-31drm/i915: Simplify pipe_mask setup even furtherVille Syrjälä1-3/+1
2019-10-31drm/i915: Allow ICL+ DSI on any pipeVille Syrjälä1-1/+3
2019-10-31drm/i915: s/crtc_mask/pipe_mask/Ville Syrjälä1-1/+1
2019-08-16drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio1-7/+4
2019-08-08drm/i915/tgl/dsi: Enable blanking packets during BLLP for video modeVandita Kulkarni1-0/+5
2019-08-08drm/i915/tgl/dsi: Gate the ddi clocks after pll mappingVandita Kulkarni1-2/+8
2019-08-08drm/i915/tgl/dsi: Do not override TA_SUREVandita Kulkarni1-12/+14
2019-08-08drm/i915/tgl/dsi: Set latency PCS_DW1 for tglVandita Kulkarni1-2/+2
2019-08-08drm/i915/tgl/dsi: Program TRANS_VBLANK registerVandita Kulkarni1-0/+9
2019-07-19drm/i915/dsi: remove set but not used variable 'hfront_porch'YueHaibing1-3/+1
2019-07-10drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespaceMatt Roper1-68/+59
2019-07-10drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHYMatt Roper1-13/+20
2019-07-09drm/i915: Add icl mipi dsi propertiesVandita Kulkarni1-0/+22
2019-06-20drm/i915/ehl/dsi: Enable AFE over PPI strapJosé Roberto de Souza1-0/+8
2019-06-20drm/i915/ehl/dsi: Set lane latency optimization for DW1Vandita Kulkarni1-0/+13
2019-06-17drm/i915: move modesetting output/encoder code under display/Jani Nikula1-0/+1589
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