aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-10-29drm/i915: Fix PCH reference clock for FDI on HSW/BDWVille Syrjälä1-0/+15
2019-08-16drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio1-33/+11
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula1-1/+1
2019-07-18drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1Vivek Kasireddy1-4/+14
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza1-2/+6
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi1-5/+19
2019-07-11drm/i915/tgl: Add pll managerVandita Kulkarni1-1/+18
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä1-12/+7
2019-07-10drm/i915: Transition port type checks to phy checksMatt Roper1-5/+6
2019-07-09drm/i915/icl: Clear the shared port PLLs from the new crtc stateImre Deak1-5/+7
2019-07-09drm/i915: Clear the shared PLL from the put_dplls() hookImre Deak1-6/+14
2019-07-05drm/i915/ehl: Add support for DPLL4 (v10)Vivek Kasireddy1-4/+43
2019-07-03drm/i915/display: Handle lost primary_port across suspendChris Wilson1-9/+4
2019-07-01drm/i915: Keep the TypeC port mode fixed when the port is activeImre Deak1-1/+27
2019-07-01drm/i915/icl: Reserve all required PLLs for TypeC portsImre Deak1-41/+112
2019-07-01drm/i915/icl: Split getting the DPLLs to port type specific functionsImre Deak1-34/+66
2019-07-01drm/i915: Sanitize the shared DPLL find/reference interfaceImre Deak1-37/+70
2019-07-01drm/i915: Sanitize the shared DPLL reserve/release interfaceImre Deak1-82/+139
2019-07-01drm/i915: Sanitize the terminology used for TypeC port modesImre Deak1-1/+1
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-0/+3359